Inventor

ALPERT CHARLES JAY

US75 patents

⚠️ This page may combine multiple inventors who share the name “ALPERT CHARLES JAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALPERT CHARLES JAY

IBM

Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation

Optimum buffer placement for noise avoidance

Porosity aware buffered steiner tree construction

Practical methodology for early buffer and wire resource allocation

Method and system for re-routing interconnects within an integrated circuit design having blockages and bays

Probabilistic congestion prediction with partial blockages

Method and system for segmenting wires prior to buffer insertion

Latch clustering with proximity to local clock buffers

Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management

Apparatus and method for determining buffered steiner trees for complex circuits

Optimal buffered routing path constructions for single and multiple clock domains systems

Stability metrics for placement to quantify the stability of placement algorithms

Physical synthesis optimization with fast metric check

Apparatus and method for buffer library selection for use in buffer insertion

Clustering techniques for faster and better placement of VLSI circuits

Latch placement technique for reduced clock signal skew

Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes

Techniques for super fast buffer insertion

Method and apparatus for diffusion based cell placement migration

Creating regional routing blockages in integrated circuit design

Buffer insertion with adaptive blockage avoidance

Two moment RC delay metric for performance optimization

Method and apparatus for performing density-biased buffer insertion in an integrated circuit design

Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique

Solving traffic congestion using vehicle grouping

Solving traffic congestion using vehicle grouping

Timing driven routing in integrated circuit design

CADENCE DESIGN SYSTEMS INC

Systems and methods for modifying a balanced clock structure

Local cluster refinement

Systems and methods for assigning clock taps based on timing

Systems and methods for clock tree clustering

System and method for constructing spanning trees

View pruning for routing tree optimization

Placement of cells in a multi-level routing tree

Region aware clustering

Balanced scaled-load clustering

Routing tree topology generation

Systems and methods for clock tree generation with buffers and inverters

Clock cell library selection

Skewing level limited clock tree

Wire density-aware layer assignment

ALPERT CHARLES JAY

Early design cycle optimzation

Latch clustering with proximity to local clock buffers

Solving congestion using net grouping

Routing and timing using layer ranges

Object placement in integrated circuit design

Solving network traffic congestion using device grouping

Congestion aware routing using random points

Solving traffic congestion using vehicle grouping

AGARWAL KANAK BEHARI

Multi-patterning lithography aware cell placement in integrated circuit design