Inventor

LI ZHUO

US171 patents

⚠️ This page may combine multiple inventors who share the name “LI ZHUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI ZHUO

CADENCE DESIGN SYSTEMS INC

Routing congestion based on fractional via cost and via density

Routing congestion based on layer-assigned net and placement blockage

Modifying route topology to fix clock tree violations

Machine-learning based clustering for clock tree synthesis

System and method for routing in an integrated circuit design

Routing framework to resolve single-entry constraint violations for integrated circuit designs

Layer assignment technique to improve timing in integrated circuit design

Post-CTS clock tree restructuring

Clock pin to clock tap assignment based on circuit device connectivity

Multicorner skew scheduling circuit design

Devices and methods for balanced routing tree structures

Irregular sink arrangement for balanced routing tree structures

Systems and methods for routing track assignment

Integrated circuit routing based on enhanced topology

Partition-aware grid graph based hierarchical global routing

Systems and methods for modifying a balanced clock structure

Systems and methods for assigning clock taps based on timing

Systems and methods for clock tree clustering

System and method for constructing spanning trees

Post-CTS clock tree restructuring with ripple move

Layer assignment based on wirelength threshold

IBM

Probabilistic congestion prediction with partial blockages

Latch clustering with proximity to local clock buffers

Fault-tolerant power-driven synthesis

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Computer-based modeling of integrated circuit congestion and wire distribution for products and services

Broken-spheres methodology for improved failure probability analysis in multi-fail regions

Automatic generation of wire tag lists for a metal stack

Automatic generation of wire tag lists for a metal stack

Resolving global coupling timing and slew violations for buffer-dominated designs

Incremental timing-driven, physical-synthesis using discrete optimization

Boundary latch and logic placement to satisfy timing constraints

Physical synthesis optimization with fast metric check

Buffer-aware routing in integrated circuit design

Concurrent buffering and layer assignment in integrated circuit layout

Techniques for super fast buffer insertion

Power-driven synthesis under latency constraints

Creating regional routing blockages in integrated circuit design

Routing centric design closure

ALPERT CHARLES J

Placement of structured nets

Clock optimization with local clock buffer control optimization

Datapath placement using tiered assignment

Consideration of local routing and pin access during VLSI global routing

ALPERT CHARLES JAY

Early design cycle optimzation

Latch clustering with proximity to local clock buffers

Solving congestion using net grouping

KAZDA MICHAEL ANTHONY

Timing refinement re-routing

AGARWAL KANAK BEHARI

Multi-patterning lithography aware cell placement in integrated circuit design

WHATSAPP INC

Verifying users of an electronic messaging system

UNIV CHINA PETROLEUM EAST CHINA

Pore pressure prediction method and system for fine-grained hybrid sedimentary rock based on variable p-wave velocity