Inventor

LOH GABRIEL H

US108 patents

⚠️ This page may combine multiple inventors who share the name “LOH GABRIEL H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOH GABRIEL H

ADVANCED MICRO DEVICES INC

Die-stacked memory device with reconfigurable logic

Page migration in a 3D stacked hybrid memory

Die-stacked memory device with reconfigurable logic

Die-stacked device with partitioned multi-hop network

Page migration in a hybrid memory device

Processor with host and slave operating modes stacked with memory

Cache with address space mapping to slice subsets

Spare memory external to protected memory

Query operations for stacked-die memory device

Die-stacked device with partitioned multi-hop network

Bypassing memory requests to a main memory

High reliability memory controller

Creating interconnects between dies using a cross-over die and through-die vias

Activation function functional block for electronic devices

Lossy significance compression with lossy restoration

Memory hierarchy using page-based compression

Mechanism for throttling untrusted interconnect agents

Hybrid cache

Computation memory operations in a logic layer of a stacked memory

Scheduling memory accesses using an efficient row burst value

Memory hierarchy using row-based compression

Translation lookaside buffer

Mechanisms to bound the presence of cache blocks with specific properties in caches

Flexible, scalable graph-processing accelerator

Data compression and encryption based on translation lookaside buffer evictions

Coherency directory entry allocation based on eviction costs

Preemptive cache management policies for processing units

Reducing cache footprint in cache coherence directory

Hot page selection in multi-level memory hierarchies

Partitioning caches for sub-entities in computing devices

Quantum circuit mapping for multi-programmed quantum computers

Conditional prefetching

Memory page access detection

Cluster-based migration in a multi-level memory hierarchy

Management of caches

Systems and methods for programmed branch predictors

Mechanism for reducing page migration overhead in memory systems

Locality-based data processing

LOH GABRIEL H

Die-stacked memory device providing data translation

Stacked memory device with metadata management

Cache coherency using die-stacked memory device with logic die

DRAM cache with tags and data jointly stored in physical rows

Cache prefetching from non-uniform memories

Uniform multi-chip identification and routing system

Hardware filter for tracking block presence in large caches

INTEL CORP

Memory array on more than one die

HSU LISA R

Quality of service support using stacked memory device with logic die

BHAGAVAT MILIND S

Multi-chip package with offset 3D structure

ATI TECHNOLOGIES ULC

Method and apparatus for translation lookaside buffer with multiple compressed encodings

ARORA MANISH

Distributed computing with phase change material thermal management