Inventor

HANEBUTTE ULF

US26 patents

⚠️ This page may combine multiple inventors who share the name “HANEBUTTE ULF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HANEBUTTE ULF

MARVELL ASIA PTE LTD

Architecture to support tanh and sigmoid operations for inference acceleration in machine learning

Method and apparatus for correlating high-level code with low-level instructions for machine learning applications

Method and apparatus for performing machine learning operations in parallel on machine learning hardware

Method and apparatus for ML graphs by a compiler

Method and apparatus for generating metadata by a compiler

Method and system for memory management within machine learning inference engine

Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardware

Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engine

Architecture to support tanh and sigmoid operations for inference acceleration in machine learning

Method and apparatus for performing machine learning operations in parallel on machine learning hardware

System and method for INT9 quantization

Method and apparatus for generating metadata by a compiler

System and method for INT9 quantization

Architecture for table-based mathematical operations for inference acceleration in machine learning

Architecture for table-based mathematical operations for inference acceleration in machine learning

Method and system for code optimization based on statistical data

Multistage compiler architecture

Method and system to expand accessible on-chip memory (OCM) of an inference engine

Method and system for compiler generated external strategies

CAVIUM LLC

Streaming engine for machine learning architecture

Architecture for dense operations in machine learning inference engine

Array-based inference engine for machine learning

Architecture of crossbar of inference engine

Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine

Architecture for irregular operations in machine learning inference engine

MARVELL ASIA PTE LTD REGISTRATION NO 199702379M

System and method for handling floating point hardware exception