Inventor

CHOU CHIEN-CHUN

US35 patents

⚠️ This page may combine multiple inventors who share the name “CHOU CHIEN-CHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOU CHIEN-CHUN

SONICS INC

Method and apparatus for speculative response arbitration to improve system latency

Composing on-chip interconnects with configurable interfaces

Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems

On-chip inter-network performance optimization using configurable performance parameters

Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets

Method and apparatus for automatic configuration of multiple on-chip interconnects

Scalable low bandwidth multicast handling in mixed core systems

Method and apparatus for error handling in networks

Method and system to monitor, debug, and analyze performance of an electronic design

Communication system and method with configurable posting points

Various methods and apparatuses for cycle accurate C-models of components

Reordering responses in a high performance on-chip network

Composing on-chip interconnects with configurable interfaces

MARVELL ASIA PTE LTD

Method and apparatus for correlating high-level code with low-level instructions for machine learning applications

Method and apparatus for ML graphs by a compiler

Method and apparatus for generating metadata by a compiler

Method and system for memory management within machine learning inference engine

Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardware

Method and apparatus for performing machine learning operations in parallel on machine learning hardware

Method and apparatus for generating metadata by a compiler

Method and system for code optimization based on statistical data

Multistage compiler architecture

Method and system for compiler generated external strategies

SRINIVASAN KRISHNAN

Various methods and apparatus for address tiling

Various methods and apparatus for address tiling and channel interleaving throughout the integrated system

Performance software instrumentation and analysis for electronic design automation

Method and system for a database to monitor and analyze performance of an electronic design

Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads

WINGARD DREW E

Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering

Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary

Interconnect implementing internal controls

CHOU CHIEN-CHUN

Methods and apparatuses for time annotated transaction level modeling

ALEXANIAN HERVE JACQUES

Transaction co-validation across abstraction layers

WEBER WOLF-DIETRICH

Method and apparatus for establishing a quality of service model

FACEBOOK TECH LLC

Reordering responses in a high performance on-chip network