Inventor

SETHURAMAN SARAVANAN

MY103 patents

⚠️ This page may combine multiple inventors who share the name “SETHURAMAN SARAVANAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SETHURAMAN SARAVANAN

IBM

Concurrent upgrade and backup of non-volatile memory

System for securing contents of removable memory

Write management for increasing non-volatile memory reliability

In-channel memory mirroring

Concurrent upgrade and backup of non-volatile memory

Thermal-aware memory

Thermal-aware memory

Detecting defective connections in stacked memory devices

Detecting defective connections in stacked memory devices

Implementing ECC redundancy using reconfigurable logic blocks

Self monitoring and self repairing ECC

Using dual channel memory as single channel memory with spares

Parallel read and writes in 3D flash memory

Concurrent upgrade and backup of non-volatile memory

Data buffer spare architectures for dual channel serial interface memories

Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks

Reference voltage calibration in memory during runtime

Performance optimization of read functions in a memory system

Data retrieval from stacked computer memory

Thermal and power memory actions

Multi-party secure global attestation

Multi-party secure global attestation

Optimizing error correcting code in three-dimensional stacked memory

Reconfigurable power distribution system for three-dimensional integrated circuits

Concurrent upgrade and backup of non-volatile memory

Mirroring in three-dimensional stacked memory

Memory operation of paired memory devices

Using dual channel memory as single channel memory with spares

Power management in multi-channel 3D stacked DRAM

Performance optimization of read functions in a memory system

Implementing enhanced reliability of systems utilizing dual port DRAM

Write management for increasing non-volatile memory reliability

Thermal and power memory actions

Dynamic write credit buffer management of non-volatile dual inline memory module

Method of reusing constraints in PCB designs

INTEL CORP

Methods and apparatus for managing thermal behavior in multichip packages

Interposer structures and methods for 2.5D and 3D packaging

Per bank refresh hazard avoidance for large scale memory

Memory module based data buffer communication bus training

Per channel thermal management techniques for stacked memory

Methods and apparatus for managing thermal behavior in multichip packages

Mode register update (MRUPD) mode

Systems and methods for accessing memory devices using virtual memory ranks

CORDERO EDGAR R

Three dimensional (3D) memory device sparing

Three dimensional(3D) memory device sparing

GLOBALFOUNDRIES INC

Stacked memory device control

LINGAMBUDI ANIL B

Cable for high speed data communications

SETHURAMAN SARAVANAN

System and method for providing efficient schematic review

BASSO CLAUDE

Translating between an ethernet protocol and a converged enhanced ethernet protocol

INTERNAT BUSINESSS MACHINES CORP

Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks