Inventor
LIU CHANGHUA
US21 patents
⚠️ This page may combine multiple inventors who share the name “LIU CHANGHUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
19 patentsUS12164147B2Dec 10, 2024
Device, method and system for optical communication with a waveguide structure and an integrated optical coupler of a photonic integrated circuit chip
INTEL CORP3 citations74
US11837534B2Dec 5, 2023
Substrate with variable height conductive and dielectric elements
INTEL CORP2 citations72
US11088103B2Aug 10, 2021
First layer interconnect first on carrier approach for EMIB patch
INTEL CORP3 citations72
US12523827B2Jan 13, 2026
Photonic integrated circuit to glass substrate alignment through dual cylindrical lens
INTEL CORP0 citations62
US12456705B2Oct 28, 2025
First layer interconnect first on carrier approach for EMIB patch
INTEL CORP0 citations62
US12354992B2Jul 8, 2025
First layer interconnect first on carrier approach for EMIB patch
INTEL CORP0 citations62
US12523826B2Jan 13, 2026
Photonic integrated circuit to glass substrate alignment through integrated cylindrical lens and waveguide structure
INTEL CORP0 citations61
US12345932B2Jul 1, 2025
Die last and waveguide last architecture for silicon photonic packaging
INTEL CORP0 citations61
US11264307B2Mar 1, 2022
Dual-damascene zero-misalignment-via process for semiconductor packaging
INTEL CORP0 citations61
US12341117B2Jun 24, 2025
Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates
INTEL CORP0 citations60
US11644757B2May 9, 2023
Method to achieve tilted patterning with a through resist thickness using projection optics
INTEL CORP0 citations60
US11506982B2Nov 22, 2022
Prism-mask for angled patterning applications
INTEL CORP0 citations58
US12298572B2May 13, 2025
Device, method and system for optical communication with a photonic integrated circuit chip and a transverse oriented lens structure
INTEL CORP0 citations52
US11586112B2Feb 21, 2023
Method to achieve tilted patterning with a through resist thickness
INTEL CORP0 citations52
US10403564B2Sep 3, 2019
Dual-damascene zero-misalignment-via process for semiconductor packaging
INTEL CORP0 citations51
US12560771B2Feb 24, 2026
Die first fan-out architecture for electric and optical integration
INTEL CORP0 citations50
US12449600B2Oct 21, 2025
Position controlled waveguides and methods of manufacturing the same
INTEL CORP0 citations50
US10438812B2Oct 8, 2019
Anisotropic etching systems and methods using a photochemically enhanced etchant
INTEL CORP0 citations48
US10078204B2Sep 18, 2018
Non-destructive 3-dimensional chemical imaging of photo-resist material
INTEL CORP0 citations39