Inventor
PRABHU ASHOK S
US34 patents
⚠️ This page may combine multiple inventors who share the name “PRABHU ASHOK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INVENSAS CORP
21 patentsUS9812402B2Nov 7, 2017
Wire bond wires for interference shielding
INVENSAS CORP30 citations97
US10115678B2Oct 30, 2018
Wire bond wires for interference shielding
INVENSAS CORP26 citations94
US9490195B1Nov 8, 2016
Wafer-level flipped die stacks with leadframes or metal foil interconnects
INVENSAS CORP27 citations94
US9984992B2May 29, 2018
Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
INVENSAS CORP27 citations93
US10559537B2Feb 11, 2020
Wire bond wires for interference shielding
INVENSAS CORP10 citations92
US9490222B1Nov 8, 2016
Wire bond wires for interference shielding
INVENSAS CORP20 citations92
US10181457B2Jan 15, 2019
Microelectronic package for wafer-level chip scale packaging with fan-out
INVENSAS CORP19 citations86
US10490528B2Nov 26, 2019
Embedded wire bond wires
INVENSAS CORP17 citations85
US10354976B2Jul 16, 2019
Dies-on-package devices and methods therefor
INVENSAS CORP6 citations84
US10043779B2Aug 7, 2018
Packaged microelectronic device for a package-on-package device
INVENSAS CORP8 citations84
US9991233B2Jun 5, 2018
Package-on-package devices with same level WLP components and methods therefor
INVENSAS CORP5 citations84
US9991235B2Jun 5, 2018
Package on-package devices with upper RDL of WLPS and methods therefor
INVENSAS CORP5 citations84
US9972609B2May 15, 2018
Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods therefor
INVENSAS CORP8 citations84
US9911718B2Mar 6, 2018
‘RDL-First’ packaged microelectronic device for a package-on-package device
INVENSAS CORP7 citations84
US10325877B2Jun 18, 2019
Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
INVENSAS CORP7 citations82
US9985007B2May 29, 2018
Package on-package devices with multiple levels and methods therefor
INVENSAS CORP3 citations73
US9972573B2May 15, 2018
Wafer-level packaged components and methods therefor
INVENSAS CORP3 citations73
US9825002B2Nov 21, 2017
Flipped die stack
INVENSAS CORP3 citations73
US9871019B2Jan 16, 2018
Flipped die stack assemblies with leadframe interconnects
INVENSAS CORP1 citations52
US9761554B2Sep 12, 2017
Ball bonding metal wire bond wires to metal pads
INVENSAS CORP0 citations52
US9666513B2May 30, 2017
Wafer-level flipped die stacks with leadframes or metal foil interconnects
INVENSAS CORP0 citations52
NAT SEMICONDUCTOR CORP
8 patentsUS7102209B1Sep 5, 2006
Substrate for use in semiconductor manufacturing and method of making same
NAT SEMICONDUCTOR CORP91 citations96
US6933597B1Aug 23, 2005
Spacer with passive components for use in multi-chip modules
NAT SEMICONDUCTOR CORP33 citations93
US6364089B1Apr 2, 2002
Multi-station rotary die handling device
NAT SEMICONDUCTOR CORP46 citations93
US8679896B2Mar 25, 2014
DC/DC converter power module package incorporating a stacked controller and construction methodology
NAT SEMICONDUCTOR CORP23 citations92
US7087986B1Aug 8, 2006
Solder pad configuration for use in a micro-array integrated circuit package
NAT SEMICONDUCTOR CORP33 citations92
US7186588B1Mar 6, 2007
Method of fabricating a micro-array integrated circuit package
NAT SEMICONDUCTOR CORP27 citations89
US7259460B1Aug 21, 2007
Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package
NAT SEMICONDUCTOR CORP21 citations88
US7064419B1Jun 20, 2006
Die attach region for use in a micro-array integrated circuit package
NAT SEMICONDUCTOR CORP23 citations88