Inventor · disambiguated record
Edward W. Sengle
Also filed as: SENGLE EDWARD W · SENGLE EDWARD WILLIAM
9 granted patents·243 citations·filing 1995–2003
90Inventor score
Files withIBM9
Top patents by PatentIndex Score
9 records- 0192US6624031B2Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structureIBM·Filed 2001·Granted Sep 23, 2003·62 cites·13 claims
- 0280US6147394AMethod of photolithographically defining three regions with one mask step and self aligned isolation structure formed therebyIBM·Filed 1998·Granted Nov 14, 2000·54 cites·1 claims
- 0377US6394638B1Trench isolation for active areas and first level conductorsIBM·Filed 2000·Granted May 28, 2002·19 cites·10 claims
- 0473US5972570AMethod of photolithographically defining three regions with one mask step and self aligned isolation structure formed therebyIBM·Filed 1997·Granted Oct 26, 1999·38 cites·19 claims
- 0568US5734192ATrench isolation for active areas and first level conductorsIBM·Filed 1995·Granted Mar 31, 1998·29 cites·20 claims
- 0666US7132325B2Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structureIBM·Filed 2003·Granted Nov 7, 2006·10 cites·19 claims
- 0761US6140171AFET device containing a conducting sidewall spacer for local interconnect and method for its fabricationIBM·Filed 1999·Granted Oct 31, 2000·26 cites·25 claims
- 0856US6770907B2Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structureIBM·Filed 2003·Granted Aug 3, 2004·5 cites·8 claims
- 0930US6063687AFormation of trench isolation for active areas and first level conductorsIBM·Filed 1997·Granted May 16, 2000·0 cites·12 claims
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