Inventor

HERSHMAN ZIV

IL47 patents

⚠️ This page may combine multiple inventors who share the name “HERSHMAN ZIV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HERSHMAN ZIV

NUVOTON TECHNOLOGY CORP

Detection of fault injection attacks

Parsimonious systems for touch detection and capacitive touch methods useful in conjunction therewith

Detection of fault injection attacks using high-fanout networks

Processor with in-band fault-injection detection

Data-sampling integrity check by sampling using flip-flops with relative delay

Data-sampling integrity check using gated clock

Device attestation including attestation-key modification following boot event

Secure IC with soft security countermeasures

Secured master-mediated transactions between slave devices using bus monitoring

Secure memory access using memory read restriction

Security device having indirect access to external non-volatile memory

Secured computing system with asynchronous authentication

Integrity verification of lifecycle-state memory using multi-threshold supply voltage detection

Digital fault injection detector

Secure system boot monitor

Secure access to peripheral devices over a bus

Secure access to peripheral devices over a bus

Security monitoring of SPI flash

Maintaining data-set coherency in non-volatile memory across power interruptions

Power analysis attack protection

Protected system

Mitigation of side-channel attacks using small-overhead random pre-charging

Random number generator based on meta-stability of shorted back-to-back inverters

Active shield portion serving as serial keypad

Tracking and prevention of fault injection attempt sequences using thermal memory

Multi-stage provisioning of secret data

PQA unlock

System and methods for increasing useful lifetime of a flash memory device

Protection against side-channel attacks by balancing cell drive polarity

Secured communication by monitoring bus transactions using selectively delayed clock signal

Coupling of combinational logic circuits for protection against side-channel attacks

System and method for correction of memory errors

Binding of TPM and root device

RPMC flash emulation

System and method for prioritization of bit error correction attempts

Reliable programming of one-time programmable (OTP) memory during device testing

Secure integrated-circuit state management

WINBOND ELECTRONICS CORP

Wakeup of a non-powered universal serial bus

Protection of memory interface

Protecting memory interface

NAT SEMICONDUCTOR CORP

Circuitry and method for detecting and protecting against over-clocking attacks

Method and apparatus for limiting the output frequency of an on-chip clock generator

GOOGLE LLC

Interface for revision-limited memory

Interface for revision-limited memory

HERSHMAN ZIV

Systems and methods for detecting multiple touch points in surface-capacitance type touch panels

STOLOV ILIA

Systems and methods for detecting multiple touch points in surface-capacitance type touch panels

NUVOTON TECH CORPORATION

Self-synchronous side-channel attack countermeasure