Inventor
TAGUE STEVEN A
US17 patents
⚠️ This page may combine multiple inventors who share the name “TAGUE STEVEN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HONEYWELL INF SYSTEMS
11 patentsUS4161784AJul 17, 1979
Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
HONEYWELL INF SYSTEMS249 citations98
US4390961AJun 28, 1983
Data processor performing a decimal multiply operation using a read only memory
HONEYWELL INF SYSTEMS33 citations92
US4484300ANov 20, 1984
Data processor having units carry and tens carry apparatus supporting a decimal multiply operation
HONEYWELL INF SYSTEMS24 citations82
US4447870AMay 8, 1984
Apparatus for setting the basic clock timing in a data processing system
HONEYWELL INF SYSTEMS24 citations82
US4426680AJan 17, 1984
Data processor using read only memories for optimizing main memory access and identifying the starting position of an operand
HONEYWELL INF SYSTEMS21 citations82
US4837738AJun 6, 1989
Address boundary detector
HONEYWELL INF SYSTEMS12 citations74
US4462072AJul 24, 1984
Clock system having a stall capability to enable processing of errors
HONEYWELL INF SYSTEMS19 citations73
US4423483ADec 27, 1983
Data processor using a read only memory for selecting a part of a register into which data is written
HONEYWELL INF SYSTEMS11 citations73
US4410984AOct 18, 1983
Diagnostic testing of the data path in a microprogrammed data processor
HONEYWELL INF SYSTEMS13 citations73
US4384341AMay 17, 1983
Data processor having carry apparatus supporting a decimal divide operation
HONEYWELL INF SYSTEMS18 citations73
US4384340AMay 17, 1983
Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions
HONEYWELL INF SYSTEMS18 citations73
BULL HN INFORMATION SYST
5 patentsUS5375248ADec 20, 1994
Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories
BULL HN INFORMATION SYST24 citations92
US5283876AFeb 1, 1994
Virtual memory unit utilizing set associative memory structure and state machine control sequencing with selective retry
BULL HN INFORMATION SYST22 citations92
US5280595AJan 18, 1994
State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
BULL HN INFORMATION SYST15 citations74
US5243601ASep 7, 1993
Apparatus and method for detecting a runaway firmware control unit
BULL HN INFORMATION SYST4 citations63
US5161217ANov 3, 1992
Buffered address stack register with parallel input registers and overflow protection
BULL HN INFORMATION SYST5 citations62