Inventor

FANDRICH MICKEY L

US36 patents

Patents

36 patents

US5519847AMay 21, 1996

Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory

INTEL CORP136 citations98

US5353256AOct 4, 1994

Block specific status information in a memory device

INTEL CORP153 citations97

US5327383AJul 5, 1994

Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy

INTEL CORP114 citations97

US5802552ASep 1, 1998

System and method for allocating and sharingpage buffers for a flash memory device

INTEL CORP96 citations96

US5592641AJan 7, 1997

Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status

INTEL CORP224 citations96

US5513333AApr 30, 1996

Circuitry and method for programming and erasing a non-volatile semiconductor memory

INTEL CORP42 citations96

US5448712ASep 5, 1995

Circuitry and method for programming and erasing a non-volatile semiconductor memory

INTEL CORP53 citations96

US5377145ADec 27, 1994

Circuitry and method for programming and erasing a non-volatile semiconductor memory

INTEL CORP61 citations96

US5377147ADec 27, 1994

Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy

INTEL CORP90 citations96

US5347489ASep 13, 1994

Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy

INTEL CORP93 citations96

US5623620AApr 22, 1997

Special test modes for a page buffer shared resource in a memory device

INTEL CORP68 citations95

US5369647ANov 29, 1994

Circuitry and method for testing a write state machine

INTEL CORP58 citations95

US5369754ANov 29, 1994

Block specific status information in a memory device

INTEL CORP103 citations94

US5224070AJun 29, 1993

Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

INTEL CORP101 citations94

US5377199ADec 27, 1994

Boundary test scheme for an intelligent device

INTEL CORP33 citations93

US5333300AJul 26, 1994

Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory

INTEL CORP52 citations93

US5748939AMay 5, 1998

Memory device with a central control bus and a control access register for translating an access request into an access cycle on the central control bus

INTEL CORP24 citations92

US5692138ANov 25, 1997

Flexible user interface circuit in a memory device

INTEL CORP43 citations92

US5546561AAug 13, 1996

Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory

INTEL CORP45 citations92

US5414829AMay 9, 1995

Override timing control circuitry and method for terminating program and erase sequences in a flash memory

INTEL CORP43 citations92

US5412793AMay 2, 1995

Method for testing erase characteristics of a flash memory array

INTEL CORP30 citations92

US5265059ANov 23, 1993

Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory

INTEL CORP44 citations92

US5249158ASep 28, 1993

Flash memory blocking architecture

INTEL CORP60 citations92

US5835927ANov 10, 1998

Special test modes for a page buffer shared resource in a memory device

INTEL CORP31 citations91

US5513136AApr 30, 1996

Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations

INTEL CORP50 citations91

US5463757AOct 31, 1995

Command interface between user commands and a memory device

INTEL CORP43 citations88

US6370651B1Apr 9, 2002

Synchronizing user commands to a microcontroller in a memory device

INTEL CORP8 citations74

US5850509ADec 15, 1998

Circuitry for propagating test mode signals associated with a memory array

INTEL CORP8 citations74

US5574850ANov 12, 1996

Circuitry and method for reconfiguring a flash memory

INTEL CORP13 citations74

US5339320AAug 16, 1994

Architecture of circuitry for generating test mode signals

INTEL CORP15 citations74

US5537357AJul 16, 1996

Method for preconditioning a nonvolatile memory array

INTEL CORP17 citations72

US7624316B2Nov 24, 2009

Apparatus and method for testing removable flash memory devices

INTEL CORP2 citations63

US5430677AJul 4, 1995

Architecture for reading information from a memory array

INTEL CORP3 citations61

FANDRICH MICKEY L

Patents

Method of pipelining sequential writes in a flash memory

Method and circuitry for queuing snooping, prioritizing and suspending commands

Method and apparatus for execution of operations in a flash memory array

Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory

Block specific status information in a memory device

Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy

System and method for allocating and sharingpage buffers for a flash memory device

Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status

Circuitry and method for programming and erasing a non-volatile semiconductor memory

Circuitry and method for programming and erasing a non-volatile semiconductor memory

Circuitry and method for programming and erasing a non-volatile semiconductor memory

Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy

Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy

Special test modes for a page buffer shared resource in a memory device

Circuitry and method for testing a write state machine

Block specific status information in a memory device

Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

Boundary test scheme for an intelligent device

Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory

Memory device with a central control bus and a control access register for translating an access request into an access cycle on the central control bus

Flexible user interface circuit in a memory device

Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory

Override timing control circuitry and method for terminating program and erase sequences in a flash memory

Method for testing erase characteristics of a flash memory array

Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory

Flash memory blocking architecture

Special test modes for a page buffer shared resource in a memory device

Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations

Command interface between user commands and a memory device

Synchronizing user commands to a microcontroller in a memory device

Circuitry for propagating test mode signals associated with a memory array

Circuitry and method for reconfiguring a flash memory

Architecture of circuitry for generating test mode signals

Method for preconditioning a nonvolatile memory array

Apparatus and method for testing removable flash memory devices

Architecture for reading information from a memory array