Inventor

SU KE-YING

TW44 patents

⚠️ This page may combine multiple inventors who share the name “SU KE-YING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SU KE-YING

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit layout generation method and system

Integrated circuit modeling methods and systems

Method of generating modified layout for RC extraction

Method and apparatus for capacitance extraction

Method for analyzing interconnect process variation

Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same

RC extraction methodology for floating silicon substrate with TSV

Multi-patterning mask decomposition method and system

Integrated circuit layout generation method and system

Integrated circuit layout generation method and system

Integrated circuit layout generation method

Integrated circuit layout generation method

Integrated circuit layout generation method and system

Method of manufacturing semiconductor device and system for same

Method of manufacturing semiconductor device and system for same

RC tool accuracy time reduction

RC tool accuracy time reduction

Method of generating modified layout and system therefor

Mask design based on sensitivities to changes in pattern spacing

Method of designing circuit layout and system for implementing the same

Method, device and computer program product for integrated circuit layout generation

Systems and methods for tuning technology files

TAIWAN SEMICONDUCTOR MFG

Parasitic capacitance extraction for FinFETs

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

Flexible pattern-oriented 3D profile for advanced process nodes

Methods and apparatus for RC extraction

Method and system for photomask assignment for double patterning technology

RC extraction for multiple patterning layout design

RC corner solutions for double patterning technology

Method of generating a simulation model of a predefined fabrication process

Method of generating RC technology file

Methods and apparatus for RC extraction

Systems and methods for creating frequency-dependent netlist

SU KE-YING

Systems and methods for creating frequency-dependent netlist

Mask-shift-aware RC extraction for double patterning design

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

RC corner solutions for double patterning technology

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

Systems and methods for creating frequency-dependent RC extraction netlist

Method of generating RC technology file

HO CHIA-MING

Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process

LU LEE-CHUNG

Mask-shift-aware RC extraction for double patterning design

WU ZE-MING

RC extraction methodology for floating silicon substrate with TSV

CHANG GWAN SIN

IC design flow enhancement with CMP simulation