Inventor

RUSSELL DAVID J

US58 patents

⚠️ This page may combine multiple inventors who share the name “RUSSELL DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RUSSELL DAVID J

IBM

Circuitry with integrated passive components and method for producing

Interconnect structure for joining a chip to a circuit card

Composition for photo imaging

Composition for photo imaging

Dual layer stack for contact formation

Process for manufacturing a multi-layer circuit board

Sequential build-up organic chip carrier and method of manufacture

Composition for photo imaging

Method of fabricating circuitized structures

Through hole in a photoimageable dielectric structure with wired and uncured dielectric

Laminate substrate having joining layer of photoimageable material

Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection

Fabrication of a metalized blind via

Aqueous soldermask

Composition for photo imaging

Composition for photo imaging

Composition for photo imaging

Printed wiring board with improved plated through hole fatigue life

Laser ablatable material and its use

Method of etching polyimides and resulting passivation structure

Laser ablatable material and its use

Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby

Reduction of solder interconnect stress

Glass interposer with embedded thermoelectric devices

Reduced-warpage laminate structure

Reduced-warpage laminate structure

Photoimageable dielectric epoxy resin system film

Method of fabricating circuitized structures

Method of forming a chip carrier by joining a laminate layer and stiffener

Fabrication of a metalized blind via

Reduction of solder interconnect stress

Semiconductor package having non-aligned active vias

Forming a through hole in a photoimageable dielectric structure

Enhanced via structure for organic module performance

Structure and method for reliability evaluation of FCPBGA substrates for high power semiconductor packaging applications

Reduced-warpage laminate structure

Coating for limiting substrate damage due to discrete failure

Coating for limiting substrate damage due to discrete failure

Interface for limiting substrate damage due to discrete failure

Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress

Printed circuit board and methods to enhance reliability

Interface for limiting substrate damage due to discrete failure

Image analysis methods for plated through hole reliability

In-plane copper imbalance for warpage prediction

Sacrificial carrier dicing of semiconductor wafers

Sacrificial carrier dicing of semiconductor wafers

KACKER KARAN

Clustered stacked vias for reliable electronic substrates

Clustered stacked vias for reliable electronic substrates

ARVIN CHARLES L

Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack

GLOBALFOUNDRIES INC

Method of forming a glass interposer with thermal vias