Inventor

OPRESCU FLORIN

US25 patents

⚠️ This page may combine multiple inventors who share the name “OPRESCU FLORIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OPRESCU FLORIN

APPLE COMPUTER

Method and apparatus for supplying power to devices coupled to a bus

Power management system for computer device interconnection bus

Methods and apparatus for bus access arbitration of nodes organized into acyclic directed graph by cyclic token passing and alternatively propagating request to root node and grant signal to the child node

System for managing power consumption of devices coupled to a common bus

Method and apparatus for unique address assignment, node self-identification and topology mapping for a directed acyclic graph

Method and apparatus for transmitting NRZ data signals across an isolation barrier disposed in an interface between adjacent devices on a bus

Method and apparatus for transforming an arbitrary topology collection of nodes into an acyclic directed graph

Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers

Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface

Adaptive clock skew and duty cycle compensation for a serial data bus

Communication node with a first bus configuration for arbitration and a second bus configuration for data transfer

CMOS differential twisted-pair driver

Delay line separator for data bus

Adaptive data separator

Method for propagating preemptive bus initialization on an acyclic directed graph

High-speed dominant mode bus for differential signals

Delay line separator for data bus

CMOS class AB amplifier for driving capacitive and resistive loads

High speed dominant mode bus for differential signals

Bus interconnect circuit including port control logic for a multiple node communication network

Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode

Method and apparatus for a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode having a full duplex, dominant logic transmission scheme

Method and apparatus for implementing a common mode level shift in a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode

CMOS differential twisted-pair driver

STEENSGAARD-MADSEN JESPER

Simultaneously-sampling single-ended and differential two-input analog-to-digital converter