Inventor

IADANZA JOSEPH ANDREW

US24 patents

⚠️ This page may combine multiple inventors who share the name “IADANZA JOSEPH ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IADANZA JOSEPH ANDREW

IBM

Programmable read ports and write ports for I/O buses in a field programmable memory array

Programmable parity checking and comparison circuit

System and method for dynamically reconfiguring a programmable gate array

Field programmable memory array

Programmable address decoder for field programmable memory array

Method of operating a field programmable memory array with a field programmable gate array

Field programmable memory array

Programmable bit line drive modes for memory arrays

Memory cells for field programmable memory array

Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array

Field programmable memory array

Field programmable memory array

System for implementing write, initialization, and reset in a memory array using a single cell write port

Programmable circuits for test and operation of programmable gate arrays

Programmable inverter circuit used in a programmable logic cell

Programmable logic cell having configurable gates and multiplexers

Process tolerant delay circuit having process sensitive and process insensitive components placed therein

Process tolerant delay circuit

Programmable logic cell

Apparatus and method for current demand distribution in electronic systems

Controllable variable delay inverter for a process tolerant delay circuit

Digital-to-analog converter using dual-gate transistors

Design structure for a digital-to-analog converter using dual-gate transistors

ARSOVSKI IGOR

Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes