Inventor
OGILVIE CLARENCE ROSSER
US22 patents
Patents
22 patentsUS6038629AMar 14, 2000
Computer system generating a processor interrupt in response to receiving an interrupt/data synchronizing signal over a data bus
IBM51 citations94
US6026471AFeb 15, 2000
Anticipating cache memory loader and method
IBM34 citations92
US5918246AJun 29, 1999
Apparatus and method for prefetching data based on information contained in a compiler generated program map
IBM25 citations92
US6260116B1Jul 10, 2001
System and method for prefetching data
IBM21 citations90
US5854908ADec 29, 1998
Computer system generating a processor interrupt in response to receiving an interrupt/data synchronizing signal over a data bus
IBM38 citations90
US7525373B1Apr 28, 2009
Compensation of process and voltage variability in multi-threshold dynamic voltage scaling circuits
IBM26 citations88
US6157981ADec 5, 2000
Real time invariant behavior cache
IBM22 citations88
US7234017B2Jun 19, 2007
Computer system architecture for a processor connected to a high speed bus transceiver
IBM14 citations81
US7480888B1Jan 20, 2009
Design structure for facilitating engineering changes in integrated circuits
IBM14 citations80
US7454642B2Nov 18, 2008
Method and architecture for power management of an electronic device
IBM7 citations71
US8347019B2Jan 1, 2013
Structure for hardware assisted bus state transition circuit using content addressable memories
IBM5 citations69
US7715995B2May 11, 2010
Design structure for measurement of power consumption within an integrated circuit
IBM3 citations62
US7330925B2Feb 12, 2008
Transaction flow control mechanism for a bus bridge
IBM2 citations62
US7275125B2Sep 25, 2007
Pipeline bit handling circuit and method for a bus bridge
IBM2 citations62
US7536496B2May 19, 2009
Method and apparatus for transmitting data in an integrated circuit
IBM2 citations61
US7831935B2Nov 9, 2010
Method and architecture for power management of an electronic device
IBM4 citations60
US6321312B1Nov 20, 2001
System and method for controlling peripheral device memory access in a data processing system
IBM2 citations60
US7787577B2Aug 31, 2010
Asynchronous interface methods and apparatus
IBM4 citations58
US7529962B1May 5, 2009
System for expanding a window of valid data
IBM3 citations55
US7289444B2Oct 30, 2007
Method for providing bounded latency in a real-time data processing system
IBM0 citations52
US7757032B2Jul 13, 2010
Computer system bus bridge
IBM0 citations50
US7469312B2Dec 23, 2008
Computer system bus bridge
IBM1 citations50