Inventor

MEHTA SUNIL D

US64 patents

⚠️ This page may combine multiple inventors who share the name “MEHTA SUNIL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEHTA SUNIL D

VANTIS CORP

Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect

Method of forming a non-volatile memory device

Floating gate memory cell structure with programming mechanism outside the read path

Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress

Method for sorting semiconductor devices having a plurality of non-volatile memory cells

Floating gate memory apparatus and method for selected programming thereof

Non-volatile memory cell having dual avalanche injection elements

Zero-power CMOS non-volatile memory cell having an avalanche injection element

Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress

Triple-well EEPROM cell using P-well for tunneling across a channel

Non-volatile memory device having a high-reliability composite insulation layer

EEPROM cell using P-well for tunneling across a channel

Avalanche injection EEPROM memory cell with P-type control gate

Boron doped silicon capacitor plate

Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide

PMOS avalanche programmed floating gate memory cell structure

Floating gate memory apparatus and method for selected programming thereof

EEPROM cell with field-edgeless tunnel window using shallow trench isolation process

Two transistor EEPROM cell using P-well for tunneling across a channel

ADVANCED MICRO DEVICES INC

Process for fabricating a high-endurance non-volatile memory device

Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss

Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide

Borderless vias on bottom metal

Borderless vias on bottom metal

Method for post transistor isolation

Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers

Method of selectively annealing damaged doped regions

Method of programming and erasing an EEPROM device under an elevated temperature and apparatus thereof

Method and apparatus incorporating nitrogen selectively for differential oxide growth

High integrity borderless vias with protective sidewall spacer

Reduction of charge loss in nonvolatile memory cells by phosphorus implantation into PECVD nitride/oxynitride films

STI punch-through defects and stress reduction by high temperature oxide reflow process

Semiconductor device having a multi-layer metal interconnect structure

Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon

Spacer-based antifuse structure for low capacitance and high reliability and method of fabrication thereof

Oxide formation process for manufacturing programmable logic device

Simplified masking process for programmable logic device manufacture

LATTICE SEMICONDUCTOR CORP

Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions

Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell

Device having electrically isolated low voltage and high voltage regions and process for fabricating the device

EEPROM with a neutralized doping at tunnel window edge

High-performance non-volatile memory device and fabrication process

Reduction of mechanical stress in shallow trench isolation process

Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb

EEPROM device having improved data retention and process for fabricating the device

Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss

EEPROM device having an isolation-bounded tunnel capacitor and fabrication process

Complementary avalanche injection EEPROM cell

Shallow junction EEPROM device and process for fabricating the device

Stacked tunneling dielectric technology for improving data retention of EEPROM cell