Inventor

MCGAHAY VINCENT J

US64 patents

⚠️ This page may combine multiple inventors who share the name “MCGAHAY VINCENT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCGAHAY VINCENT J

IBM

Device and methodology for reducing effective dielectric constant in semiconductor devices

Damascene etchback for low ε dielectric

Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits

Crackstop and oxygen barrier for low-K dielectric integrated circuits

Integrated circuit having resistor between BEOL interconnect and FEOL structure and related method

Device and methodology for reducing effective dielectric constant in semiconductor devices

Reliable BEOL integration process with direct CMP of porous SiCOH dielectric

Crackstop with release layer for crack control in semiconductors

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

Building metal pillars in a chip for structure support

Method for improving adhesion to copper

On-chip decoupling capacitor with bottom hardmask

Method for improving adhesion to copper

Single and multilevel rework

Single and multilevel rework

Dual damascene flowable oxide insulation structure and metallic barrier

Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step

Device and methodology for reducing effective dielectric constant in semiconductor devices

Method and structure for integrating MIM capacitors within dual damascene processing techniques

Hardmask for reliability of silicon based dielectrics

Structure and method for reducing thermo-mechanical stress in stacked vias

Time temperature monitoring system

Time temperature monitoring system

Method to create air gaps using non-plasma processes to damage ILD materials

Device and methodology for reducing effective dielectric constant in semiconductor devices

Building metal pillars in a chip for structure support

Integrated circuit barrierless microfluidic channel

Method of forming an on-chip decoupling capacitor with bottom hardmask

In situ formation of protective layer on silsesquioxane dielectric for dual damascene process

Interim oxidation of silsesquioxane dielectric for dual damascene process

Dual damascene flowable oxide insulation structure and metallic barrier

Structure for determining thermal cycle reliability

Method and structure for determining thermal cycle reliability

Electrical circuit odometer sensor array

Run-time dispatch system for enhanced product characterization capability

Reliable BEOL integration process with direct CMP of porous SiCOH dielectric

Hardmask for improved reliability of silicon based dielectrics

Reducing damage to ulk dielectric during cross-linked polymer removal

Interlevel dielectric layer and metal layer sealing

Interim oxidation of silsesquioxane dielectric for dual damascene process

GLOBALFOUNDRIES INC

Segmented guard-ring and chip edge seals

Seal ring structure of integrated circuit and method of forming same

Crackstop structures

Methods to form conductive thin film structures

GLOBALFOUNDRIES US INC

Dual dielectric layer for closing seam in air gap structure

Method to form air gap structure with dual dielectric layer

Manufacturing method for an artificially oriented piezoelectric film for integrated filters

EDELSTEIN DANIEL C

Reducing effective dielectric constant in semiconductor devices

MCGAHAY VINCENT J

Semiconductor article having a through silicon via and guard ring

ANGYAL MATTHEW S

Deep trench crackstops under contacts