Inventor

VENKATESAN SURESH

US68 patents

⚠️ This page may combine multiple inventors who share the name “VENKATESAN SURESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENKATESAN SURESH

POET TECH INC

Vertical cavity surface emitting laser

Self-aligned structure and method on interposer-based PIC

Methods for optical dielectric waveguide subassembly structure

Optical dielectric waveguide subassembly structures

Loopback waveguide

Optical dielectric planar waveguide process

Self-aligned structure and method on interposer-based PIC

Self-aligned structure and method on interposer-based PIC

Planar laser structure with vertical signal transition

Structure and method for testing of PIC with an upturned mirror

Loopback waveguide

Loopback waveguide

Structure and method for testing of PIC with an upturned mirror

Optical dielectric waveguide subassembly structures

Structure and method for testing of PIC with an upturned mirror

Loopback waveguide

Dual core waveguide

Dual core waveguide

Methods for optical dielectric waveguide structures

Methods for optical dielectric waveguide structure

Optical dielectric waveguide subassembly structures

MOTOROLA INC

Method for forming a semiconductor device

Integrated circuit having both vertical and horizontal devices and process for making the same

Method for forming a dual inlaid copper interconnect structure

Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

Process for fabricating a fully self-aligned soi mosfet

Method of forming semiconductor device including interconnect barrier layers

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

Method for making CMOS device having reduced parasitic capacitance

Process for fabricating a semiconductor device using dual planarization layers

Method for forming a dual inlaid copper interconnect structure

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

RASHED MAHBUB

Cross-coupling based design using diffusion contact structures

Semiconductor device with transistor local interconnects

Semiconductor device with transistor local interconnects

Methods of using a trench salicide routing layer

Middle-of-the-line constructs using diffusion contact structures

Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same

GLOBALFOUNDRIES INC

Densely packed standard cells for integrated circuit products, and methods of making same

Semiconductor device with transistor local interconnects

Variable power rail design

PURDUE RESEARCH FOUNDATION

Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor

Dual-gated semiconductor-on-insulator field effect transistor

FREESCALE SEMICONDUCTOR INC

Process for forming an electronic device including semiconductor fins

Deep STI trench and SOI undercut enabling STI oxide stressor

GLOBALFOUNDRIES US INC

Semiconductor device with transistor local interconnects

Semiconductor device with transistor local interconnects

ORLOWSKI MARIUS K

Method and apparatus for mobility enhancement in a semiconductor device

SHIKARI FAIYAZ

Intelligent work load manager