Inventor
PERERA ASANGA H
US23 patents
⚠️ This page may combine multiple inventors who share the name “PERERA ASANGA H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
9 patentsUS8901632B1Dec 2, 2014
Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology
FREESCALE SEMICONDUCTOR INC40 citations94
US9082837B2Jul 14, 2015
Nonvolatile memory bitcell with inlaid high k metal select gate
FREESCALE SEMICONDUCTOR INC25 citations92
US8969940B1Mar 3, 2015
Method of gate strapping in split-gate memory cell with inlaid gate
FREESCALE SEMICONDUCTOR INC21 citations92
US9275864B2Mar 1, 2016
Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates
FREESCALE SEMICONDUCTOR INC19 citations84
US9142566B2Sep 22, 2015
Method of forming different voltage devices with high-K metal gate
FREESCALE SEMICONDUCTOR INC10 citations84
US9136129B2Sep 15, 2015
Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology
FREESCALE SEMICONDUCTOR INC10 citations84
US9129855B2Sep 8, 2015
Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology
FREESCALE SEMICONDUCTOR INC7 citations84
US9368499B2Jun 14, 2016
Method of forming different voltage devices with high-k metal gate
FREESCALE SEMICONDUCTOR INC5 citations73
US9728410B2Aug 8, 2017
Split-gate non-volatile memory (NVM) cell and method therefor
FREESCALE SEMICONDUCTOR INC0 citations42
PERERA ASANGA H
7 patentsUS8871598B1Oct 28, 2014
Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology
PERERA ASANGA H23 citations92
US8877585B1Nov 4, 2014
Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration
PERERA ASANGA H11 citations84
US9082650B2Jul 14, 2015
Integrated split gate non-volatile memory cell and logic structure
PERERA ASANGA H7 citations83
US9136360B1Sep 15, 2015
Methods and structures for charge storage isolation in split-gate memory arrays
PERERA ASANGA H4 citations72
US9318568B2Apr 19, 2016
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
PERERA ASANGA H2 citations62
US9252246B2Feb 2, 2016
Integrated split gate non-volatile memory cell and logic device
PERERA ASANGA H2 citations62
US9105748B1Aug 11, 2015
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
PERERA ASANGA H3 citations62
MOTOROLA INC
5 patentsUS6362057B1Mar 26, 2002
Method for forming a semiconductor device
MOTOROLA INC313 citations99
US6524931B1Feb 25, 2003
Method for forming a trench isolation structure in an integrated circuit
MOTOROLA INC83 citations98
US5786263AJul 28, 1998
Method for forming a trench isolation structure in an integrated circuit
MOTOROLA INC149 citations98
US5665202ASep 9, 1997
Multi-step planarization process using polishing at two different pad pressures
MOTOROLA INC103 citations97
US5698893ADec 16, 1997
Static-random-access memory cell with trench transistor and enhanced stability
MOTOROLA INC34 citations86