Inventor

SUDIJONO JOHN

SG48 patents

⚠️ This page may combine multiple inventors who share the name “SUDIJONO JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUDIJONO JOHN

CHARTERED SEMICONDUCTOR MFG

Copper recess formation using chemical process for fabricating barrier cap for lines and vias

Two-step, low argon, HDP CVD oxide deposition process

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Use of amorphous carbon as a removable ARC material for dual damascene fabrication

Method to create copper traps by modifying treatment on the dielectrics surface

Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Intermetal dielectric layer for integrated circuits

Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication

Method to remove copper contamination by using downstream oxygen and chelating agent plasma

Composite stress spacer

Composite barrier/etch stop layer comprising oxygen doped SiC and SiC for interconnect structures

Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding

Process without post-etch cleaning-converting polymer and by-products into an inert layer

Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to ≦0.10 microns

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding

Spacer-less low-k dielectric processes

Intermetal dielectric layer for integrated circuits

Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon

He treatment to improve low-k adhesion property

Method to thin down copper barriers in deep submicron geometries by using alkaline earth element, barrier additives, or self assembly technique

Method to form alpha phase Ta and its application to IC manufacturing

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding

APPLIED MATERIALS INC

Semiconductor device patterning methods

Molybdenum(0) precursors for deposition of molybdenum films

Chalcogen precursors for deposition of silicon nitride

Low temperature growth of transition metal chalcogenides

Selective deposition of a passivation film on a metal surface

Area-selective atomic layer deposition of passivation layers

Molybdenum(0) precursors for deposition of molybdenum films

Area selective carbon-based film deposition

Methods to reduce UNCD film roughness

In situ nucleation for nanocrystalline diamond film deposition

Vapor-phase precursor seeding for diamond film deposition

Tribological properties of diamond films

Tribological properties of diamond films

Resistance-switching polymer films and methods of manufacture

Oxidants and strained-ring precursors

Nanocrystalline diamond with amorphous interfacial layer

Chalcogen precursors for deposition of silicon nitride

Method of forming a diamond film

Isotropic silicon nitride removal

SEAH BOON MENG

Apparatus and methods for cleaning and drying of wafers

LEE YONG MENG

Spacer-less low-K dielectric processes

GLOBALFOUNDRIES SG PTE LTD

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

ZHAO FENG

Polishing method with inert gas injection