Inventor

NING XIAN J

US36 patents

⚠️ This page may combine multiple inventors who share the name “NING XIAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NING XIAN J

INFINEON TECHNOLOGIES AG

Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation

Self-aligned conductive line for cross-point magnetic memory integrated circuits

Self-aligned cross-point MRAM device with aluminum metallization layers

MIM capacitor structures and fabrication methods in dual-damascene structures

Method of fabricating a metal-insulator-metal (MIM) capacitor

Self-aligned double-sided vertical MIMcap

Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs

MRAM MTJ stack to conductive line alignment method

Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing

Design of lithography alignment and overlay measurement marks on CMP finished damascene surface

Method of fabricating an integrated circuit having embedded vertical capacitor

Vertical MIMCap manufacturing method

Plate-through hard mask for MRAM devices

Method for generating alignment marks for manufacturing MIM capacitors

Stacked MIMCap between Cu dual damascene levels

Single RIE process for MIMcap top and bottom plates

SEMICONDUCTOR MFG INT SHANGHAI

Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon

Metal hard mask method and structure for strained silicon MOS transistors

Method and structure for second spacer formation for strained silicon MOS transistors

Integration scheme method and structure for transistors using strained silicon

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices

Seal ring structures with unlanded via stacks

Polysilicon gate doping method and structure for strained silicon MOS transistors

Bond pad for low K dielectric materials and method for manufacture for semiconductor devices

Seal ring corner design

SIEMENS AG

Wafer surface cleaning apparatus and method

Dual damascene with bond pads

Method for detecting under-etched vias

INFINEON TECHNOLOGIES CORP

Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines

Dry process for cleaning residues/polymers after metal etch

NING XIAN J

Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices

Bond pad for low K dielectric materials and method for manufacture for semiconductor devices

IBM

Method for making a metal-insulator-metal capacitor using plate-through mask techniques

WU HANMING

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

JU JIANHUA

Method for circuit layout and rapid thermal annealing method for semiconductor apparatus