Inventor
NGUYEN PHI L
US6 patents
Patents
6 patentsUS6958547B2Oct 25, 2005
Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
INTEL CORP71 citations97
US7008872B2Mar 7, 2006
Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
INTEL CORP59 citations95
US5843846ADec 1, 1998
Etch process to produce rounded top corners for sub-micron silicon trench applications
INTEL CORP76 citations92
US6472315B2Oct 29, 2002
Method of via patterning utilizing hard mask and stripping patterning material at low temperature
INTEL CORP24 citations91
US6001699ADec 14, 1999
Highly selective etch process for submicron contacts
INTEL CORP24 citations90
US5933759AAug 3, 1999
Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications
INTEL CORP37 citations90