Inventor
KAWASHIMA SHIGEO
JP3 patents
Patents
3 patentsUS5366933ANov 22, 1994
Method for constructing a dual sided, wire bonded integrated circuit chip package
INTEL CORP120 citations94
US5545922AAug 13, 1996
Dual sided integrated circuit chip package with offset wire bonds and support block cavities
INTEL CORP92 citations93
US5527740AJun 18, 1996
Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
INTEL CORP74 citations93