Inventor

BURNETT JAMES D

US54 patents

⚠️ This page may combine multiple inventors who share the name “BURNETT JAMES D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BURNETT JAMES D

FREESCALE SEMICONDUCTOR INC

One transistor DRAM cell structure and method for forming

Integrated circuit having a memory with low voltage read/write operation

Methods for programming a floating body nonvolatile memory

Single transistor memory cell with reduced programming voltages

Interlayer dielectric under stress for an integrated circuit

Integrated circuit using FinFETs and having a static random access memory (SRAM)

Circuit and method for optimizing memory sense amplifier timing

Process for forming an electronic device including a fin-type structure

Integrated circuit having a memory with low voltage read/write operation

Word line driver circuit for a static random access memory and method therefor

Memory having self-timed bit line boost circuit and method therefor

Transistor with immersed contacts and methods of forming thereof

Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array

Apparatus and method for adjusting an operating parameter of an integrated circuit

Multiple device types including an inverted-T channel transistor and method therefor

Electronic device including a static-random-access memory cell and a process of forming the electronic device

Switch device and method

Method of forming an integrated circuit

Electronic device and method for operating a memory circuit

Integrated circuit having an embedded memory and method for testing the memory

Two-port SRAM having improved write operation

Memory access with consecutive addresses corresponding to different rows

Single transistor memory cell with reduced recombination rates

Process for forming an electronic device including a fin-type transistor structure

Transistor with asymmetry for data storage circuitry

Electronic device including a fin-type transistor structure and a process for forming the electronic device

One transistor DRAM cell structure

Single transistor memory cell with reduced recombination rates

Semiconductor structure with reduced gate doping and methods for forming thereof

Isolation trench perimeter implant for threshold voltage control

Method for forming a semiconductor device having a notched control electrode and structure thereof

Methods and structures for multiport memory devices

Memory with recessed devices

MOTOROLA INC

Write operation for capacitorless RAM

Insulated gate semiconductor device and method of manufacture

Multi-bit non-volatile memory cell and method therefor

PELLEY PERRY H

Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage

Methods and structures for multiport memory devices

Systems and methods for reduced coupling between digital signal lines

HOEFLER ALEXANDER B

Multiport single transistor bit cell

Memory having a latching sense amplifier resistant to negative bias temperature instability and method therefor

ZHANG SHAYAN

Voltage-based memory size scaling in a data processing system

Methods for testing a memory embedded in an integrated circuit

YANG JIANAN

Method and apparatus for sensing on-chip characteristics

Single event latch-up prevention techniques for a semiconductor device

BURNETT JAMES D

SRAM bit cell with reduced bit line pre-charge voltage

Method for forming one transistor DRAM cell structure

EVANS MACK N

Insecticidal collar for animals

ORLOWSKI MARIUS K

Transistors with immersed contacts

MIN BYOUNG L

Multiple device types including an inverted-T channel transistor and method therefor