Inventor

SHAH MANISH K

US70 patents

⚠️ This page may combine multiple inventors who share the name “SHAH MANISH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAH MANISH K

SAMBANOVA SYSTEMS INC

Configuration load of a reconfigurable data processor

Virtualization of a reconfigurable data processor

Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Configuration of a reconfigurable data processor using sub-files

Routing circuits for defect repair for a reconfigurable data processor

Control flow barrier and reconfigurable data processor

Defect repair circuits for a reconfigurable data processor

Quiesce reconfigurable data processor

Runtime execution of functions across reconfigurable processor

Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers

Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers

Runtime execution of configuration files on reconfigurable processors with varying configuration granularity

Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Fast argument load in a reconfigurable data processor

Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers

Force quit of reconfigurable processor

Switch for routing data in an array of functional configurable units

Defect repair for a reconfigurable data processor for homogeneous subarrays

Virtualization of a reconfigurable data processor

Configuration unload of a reconfigurable data processor

Runtime patching of configuration files

Peer-to-peer route through in a reconfigurable computing system

Peer-to-peer communication between reconfigurable dataflow units

Reconfigurable data processor with fast argument load using a runtime program on a host processor

Non-uniform memory interleave method

Fractional force-quit for reconfigurable processors

Configurable access to a reconfigurable processor by a virtual function

Handling interrupts from a virtual function in a system with a Multi-Die reconfigurable processor

Configurable access to a multi-die reconfigurable processor by a virtual function

Handling interrupts from a virtual function in a system with a reconfigurable processor

Top level network and array level network for reconfigurable data processors

Non-uniform memory interleaving processor

Avoiding use of a subarray of configurable units having a defect

Efficient deconfiguration of a reconfigurable data processor

Logic unit for a reconfigurable processor

Quiesce reconfigurable data processor

Defect avoidance in a multidimensional array of functional configurable units

Independent control of multiple concurrent application graphs in a reconfigurable data processor

SUN MICROSYSTEMS INC

Handling duplicate cache misses in a multithreaded/multi-core processor

Multiple-core processor with flexible mapping of processor cores to cache banks

Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores

Hardware demapping of TLBs shared by multiple threads

Cache error handling in a multithreaded/multi-core processor

OLSON CHRISTOPHER H

Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage

Suppressing branch prediction information update by branch instructions in incorrect speculative execution path

SHAH MANISH K

Return address prediction in multithreaded processors

Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor

ORACLE AMERICA INC

Arbitrating cache misses in a multithreaded/multi-core processor

MICROSOFT TECHNOLOGY LICENSING LLC

Charging circuit for battery-powered device

LEVINSKY GIDEON N

Dynamic sizing of translation lookaside buffer for power reduction