Inventor

GONGWER GEOFFREY S

US39 patents

⚠️ This page may combine multiple inventors who share the name “GONGWER GEOFFREY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GONGWER GEOFFREY S

SANDISK CORP

Smart verify for multi-state memories

Tracking cells for a memory system

Smart verify for multi-state memories

Noise reduction technique for transistors and small devices utilizing an episodic agitation

Symbol frequency leveling in a storage system

Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data

Efficient read, write methods for multi-state memory

Error management for writable tracking storage units

Writable tracking cells

Writable tracking cells

Selective application of program inhibit schemes in non-volatile memory

Selective program voltage ramp rates in non-volatile memory

Noise reduction technique for transistors and small devices utilizing an episodic agitation

Noise reduction technique for transistors and small devices utilizing an episodic agitation

Data recovery in a memory system using tracking cells

Symbol frequency leveling in a storage system

Writable tracking cells

Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data

Methods for writing non-volatile memories for increased endurance

Tracking cells for a memory system

Smart verify for multi-state memories

System and method for achieving fast switching of analog voltages on large capacitive load

Tracking cells for a memory system

ATMEL CORP

Input/output transistors with optimized ESD protection

Configuration control in a programmable logic device using non-volatile elements

Programmable logic device with regional and universal signal routing

Low power logic array device

Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer

Programmable logic device with global and local product terms

Boundary scan system with address dependent instructions

Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations

Integrated logic circuit with functionally flexible input/output macrocells

Voltage limiting device having improved gate-aided breakdown

Programmable logic device with multiple shared logic arrays

Logic output control circuit for a latch

Clock selection for storage elements of integrated circuits

Boundary scan method for terminating or modifying integrated circuit operating modes

GUTERMAN DANIEL C

Tracking cells for a memory system

Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data