Inventor

HESS GREG M

US40 patents

⚠️ This page may combine multiple inventors who share the name “HESS GREG M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HESS GREG M

APPLE INC

Level shifter with embedded logic and low minimum voltage

Efficient retention flop utilizing different voltage domain

Power grid segmentation for memory arrays

Zero keeper circuit with full design-for-test coverage

Efficient retention flop utilizing different voltage domain

Leakage and NBTI reduction technique for memory

Low leakage power switch

Pulsed sub-VDD precharging of a bit line

Keeperless fully complementary static selection circuit

Level shifter with embedded logic and low minimum voltage

System control using sparse data

System control using sparse data

System control using sparse data

Dynamic global memory bit line usage as storage node

Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch

Method and circuits for low latency initialization of static random access memory

System control using sparse data

Mechanism for measuring read current variability of SRAM cells

Power switch multiplexer with configurable overlap

Selectable phase or cycle jitter detector

Register file write ring oscillator

Selectable phase or cycle jitter detector

Sense amplifier soft-fail detection circuit

Memory bit cell for in-memory computation

Supply tracking delay element in multiple power domain designs

Shared gate fed sense amplifier

Configurable voltage reduction for register file

Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array

HESS GREG M

Method and apparatus for power domain isolation during power down

Passgate for dynamic circuitry

Multiplexer with level shifter

Low power memory array column redundancy mechanism

CAMPBELL BRIAN J

Level shifter with embedded logic and low minimum voltage

Leakage and NBTI reduction technique for memory

Cache optimizations using multiple threshold voltage transistors

Leakage and NBTI reduction technique for memory

PA SEMI INC

Digital leakage detector that detects transistor leakage current in an integrated circuit

Digital jitter detector

BURNETTE JAMES E

Dynamic level shifter circuit and ring oscillator using the same

KANNAN HARI S

Efficient handling of misaligned loads and stores