Inventor
KRIEGEL JON K
US27 patents
⚠️ This page may combine multiple inventors who share the name “KRIEGEL JON K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS7089341B2Aug 8, 2006
Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platform
IBM54 citations96
US8726295B2May 13, 2014
Network on chip with an I/O accelerator
IBM40 citations94
US7913010B2Mar 22, 2011
Network on chip with a low latency, high bandwidth application messaging interconnect
IBM31 citations92
US7818503B2Oct 19, 2010
Method and apparatus for memory utilization
IBM17 citations92
US7305524B2Dec 4, 2007
Snoop filter directory mechanism in coherency shared memory system
IBM37 citations92
US7552236B2Jun 23, 2009
Routing interrupts in a multi-node system
IBM21 citations91
US10318435B2Jun 11, 2019
Ensuring forward progress for nested translations in a memory management unit
IBM6 citations84
US7752413B2Jul 6, 2010
Method and apparatus for communicating between threads
IBM11 citations84
US7681020B2Mar 16, 2010
Context switching and synchronization
IBM10 citations84
US11422947B2Aug 23, 2022
Determining page size via page table cache
IBM2 citations71
US11734188B2Aug 22, 2023
Unified translation miss queue for multiple address translation modes
IBM0 citations59
US10380031B2Aug 13, 2019
Ensuring forward progress for nested translations in a memory management unit
IBM0 citations52
US7840757B2Nov 23, 2010
Method and apparatus for providing high speed memory for a processing unit
IBM0 citations52
US7577794B2Aug 18, 2009
Low latency coherency protocol for a multi-chip multiprocessor system
IBM1 citations52
US11221957B2Jan 11, 2022
Promotion of ERAT cache entries
IBM0 citations50
US11636043B2Apr 25, 2023
Sleeping and waking-up address translation that conflicts with translation level of active page table walks
IBM0 citations49
US11556475B2Jan 17, 2023
Power optimized prefetching in set-associative translation lookaside buffer structure
IBM0 citations49
KRIEGEL JON K
3 patentsHOOVER RUSSELL D
2 patentsCHEN DONG
2 patentsFRANKE HUBERTUS
2 patentsUS8688953B2Apr 1, 2014
Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities
FRANKE HUBERTUS8 citations83
US8275971B2Sep 25, 2012
Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities
FRANKE HUBERTUS8 citations83