Inventor

KIM JAEHA

US40 patents

⚠️ This page may combine multiple inventors who share the name “KIM JAEHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM JAEHA

RAMBUS INC

Receiver with enhanced clock and data recovery

Apparatus and method for controllably injecting jitter into recovered clock to simulate presence of jitter in input signal

Receiver with enhanced clock and data recovery

Optimized power supply for an electronic system

Integrated circuit having receiver jitter tolerance (“JTOL”) measurement

Receiver with enhanced clock and data recovery

Receiver with enhanced clock and data recovery

Receiver with enhanced clock and data recovery

Decision feedback equalizer

Integrated circuit having receiver jitter tolerance (“JTOL”) measurement

Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal

Decision feedback equalizer

Decision feedback equalizer

Methods and systems for transmitting data by modulating transmitter filter coefficients

KIM JAEHA

Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency

Transforming variable domains for linear circuit analysis

Hardware and method to test phase linearity of phase synthesizer

Methods and systems for transmitting data by modulating transmitter filter coefficients

Stochastic steady state circuit analyses

Process-independent schema library

LEE HAE-CHANG

Receiver with enhanced clock and data recovery

Integrated circuit having receiver jitter tolerance (“JTOL”) measurement

Integrated circuit having receiver jitter tolerance (“JTOL”) measurement

SAMSUNG ELECTRONICS CO LTD

Analog-to-digital conversion

Power supply and gate driver therein

Equalizers, communication systems and operating methods thereof

LIN QI

Signaling with superimposed differential-mode and common-mode signals

Signaling with superimposed clock and data signals

TRUE CIRCUITS INC

Delay-locked loop with dynamically biased charge pump

Delay-locked loop with dynamically biased charge pump

LEIBOWITZ BRIAN S

Decision feedback equalizer

Apparatus and methods for differential signal receiving

SILICON IMAGE INC

Clock-edge modulated serial link with DC-balance control

Adaptive bandwidth phase locked loop with feedforward divider

SEOUL NAT UNIV R&DB FOUNDATION

Neural array having multiple layers stacked therein for deep belief network and method for operating neural array

Neuron device and integrated circuit including neuron device

KOREA INST SCI & TECH

Vibrating apparatus, system and method for generating tactile stimulation

ZERBE JARED LEVAN

Optimized power supply for an electronic system

UNIV LELAND STANFORD JUNIOR

Time-based digitizer for PET photodetector

SK HYNIX INC

Circuit module for modelling a digital circuit and simulation device including the circuit module