Inventor

LEIBOWITZ BRIAN S

US127 patents

⚠️ This page may combine multiple inventors who share the name “LEIBOWITZ BRIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEIBOWITZ BRIAN S

RAMBUS INC

Memory device comprising programmable command-and-address and/or data interfaces

Methods and circuits for asymmetric distribution of channel equalization between devices

High capacity memory systems with inter-rank skew tolerance

Methods and circuits for asymmetric distribution of channel equalization between devices

Fast-wake memory control

Memory device comprising programmable command-and-address and/or data interfaces

Memory device comprising programmable command-and-address and/or data interfaces

Methods and circuits for asymmetric distribution of channel equalization between devices

Memory component with multiple command/address sampling modes

Frequency-agile clock multiplier

High-speed signaling systems and methods with adaptable, continuous-time equalization

Method and apparatus for source-synchronous signaling

Run-time output clock determination

Memory device comprising programmable command-and-address and/or data interfaces

Edge based partial response equalization

Methods and circuits for asymmetric distribution of channel equalization between devices

High-speed signaling systems and methods with adaptable, continuous-time equalization

Memory control component with inter-rank skew tolerance

Reduced-overhead error detection and correction

Method and apparatus for source-synchronous signaling

Memory device comprising programmable command-and-address and/or data interfaces

Jitter-based clock selection

Reduced-overhead error detection and correction

Methods and circuits for asymmetric distribution of channel equalization between devices

High-speed signaling systems and methods with adaptable, continuous-time equalization

Low-latency, frequency-agile clock multiplier

Fast-wake memory

Methods and circuits for asymmetric distribution of channel equalization between devices

Clock and data recovery using receiver clock spread spectrum modulation and offset compensation

DFE margin test methods and circuits that decouple sample and feedback timing

Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

Crosstalk reduction coding schemes

On-chip regulator with variable load compensation

ZERBE JARED L

High-speed signaling systems with adaptable pre-emphasis and equalization

Low-latency, frequency-agile clock multiplier

Method and apparatus for source-synchronous signaling

Receiver with time-varying threshold voltage

High-speed signaling systems with adaptable pre-emphasis and equalization

Methods and circuits for asymmetric distribution of channel equalization between devices

LEIBOWITZ BRIAN S

On-chip regulator with variable load compensation

Decision feedback equalizer

Apparatus and methods for differential signal receiving

Partial response decision-feedback equalization with adaptation based on edge samples

Method and apparatus for power sequence timing to mitigate supply resonance in power distribution network

WARE FREDERICK A

Fast-wake memory

Frequency-agile strobe window generation

LIN QI

Signaling with superimposed differential-mode and common-mode signals

OH KYUNG SUK

Asymmetric communication on shared links

LEE HAE-CHANG

Clock and data recovery employing piece-wise estimation on the derivative of the frequency

ALEKSIC MARKO

Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator