Inventor

GRISENTHWAITE RICHARD ROY

GB121 patents

⚠️ This page may combine multiple inventors who share the name “GRISENTHWAITE RICHARD ROY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRISENTHWAITE RICHARD ROY

ADVANCED RISC MACH LTD

Reducing the size of a data stream produced during instruction tracing

Cache management within a data processing apparatus

Data processing apparatus having memory protection unit

Synchronising pipelines in a data processing apparatus

Method and apparatus for placing at least one processor into a power saving mode when another processor has access to a shared resource and exiting the power saving mode upon notification that the shared resource is no longer required by the other processor

Accessing data values in a cache

Exception handling in a data processing apparatus having a secure domain and a less secure domain

Apparatus and method for handling exception events

Memory domain based security control with data processing systems

Trace data timestamping

Management of polling loops in a data processing apparatus

Interrupt controller utilising programmable priority values

Handling interrupts during multiple access program instructions

Protected function calling

Data transfer between an external data source and a memory associated with a data processor

Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits

Exclusive access control to a processing resource

Memory access prediction in a data processing apparatus

Asynchronous testing of reset operation in an integrated circuit

Programmable mapping of guard tag storage locations

Speculative cache storage region

Deferred system error exception handling in a data processing apparatus

Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory

Data structure processing

Apparatus and method for controlling use of bounded pointers

Apparatus and method for address translation and control of whether an access request is rejected based on an ownership table indicating an owner process for a block of physical addresses

Protected exception handling

Determine whether to fuse move prefix instruction and immediately following instruction independently of detecting identical destination registers

Secure initialisation

Debugging data processing transactions

Handling memory access protection and address translation in a data processing apparatus

Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction

Bus transaction management within data processing systems

Communication transaction control between independent domains of an integrated circuit

Memory interface having data signal path and tag signal path

Speculation barrier instruction

Virtualisation supporting guest operating systems using memory protection units to determine permission of a memory access operation for a physical address

GRISENTHWAITE RICHARD ROY

Stack pointer and memory access alignment control

Apparatus and method for handling exception events

Mapping between registers used by multiple instruction sets

Illegal mode change handling

WILLIAMS MICHAEL JOHN

Debugging of a data processing apparatus

Diagnosing code using single step execution

Controlling generation of debug exceptions

MANSELL DAVID HENNAH

Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty

Data processing apparatus and method for handling address translation for access requests issued by processing circuitry

PIRY FREDERIC CLAUDE MARIE

Handling of write access requests to shared memory in a data processing apparatus

RIOCREUX PETER ANDREW

Synchronising activities of various components in a distributed system

GREENHALGH PETER RICHARD

Virtualization software migrating workload between processing circuitries while making architectural states available transparent to operating system

GILDAY DAVID MICHAEL

Alias management within a virtually indexed and physically tagged cache memory