Inventor
SURPRISE JESSE P
US5 patents
Patents
5 patentsUS9684756B1Jun 20, 2017
Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design
IBM9 citations77
US9934341B2Apr 3, 2018
Simulation of modifications to microprocessor design
IBM2 citations69
US10719654B2Jul 21, 2020
Placement and timing aware wire tagging
IBM1 citations55
US9928322B2Mar 27, 2018
Simulation of modifications to microprocessor design
IBM0 citations48
US10042972B2Aug 7, 2018
Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design
IBM0 citations42