Inventor

RABINOVITCH ALEXANDER

IL46 patents

⚠️ This page may combine multiple inventors who share the name “RABINOVITCH ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RABINOVITCH ALEXANDER

SYNOPSYS INC

Efficient waveform generation for emulation

Transformations for multicycle path prediction of clock signals

X-propagation in emulation using efficient memory

Efficient waveform generation for emulation

System and method for optimizing emulation throughput by selective application of a clock pattern

Partitioning and routing multi-SLR FPGA for emulation and prototyping

Preemptive stoppage of design clocks for processing blocking direct programming interface calls

Clock signal realignment for emulation of a circuit design

Multicycle path prediction of reset signals

Method and system for emulation clock tree reduction

Method and apparatus for emulation and prototyping with variable cycle speed

Method for compression of emulation time line in presence of dynamic re-programming of clocks

Waveform capture using multicycle path properties

Deterministic identifiers for source code elements

X-propagation in emulation using efficient memory

X-propagation in emulation

Method and apparatus for emulation and prototyping with variable cycle speed

Method and apparatus for modeling delays in emulation

Method and apparatus for modeling delays in emulation

Overlaying of clock and data propagation in emulation

Efficient resolution of latch race conditions in emulation

RABINOVITCH ALEXANDER

Cache replacement using active cache line counters

Compact circuit-simulation output

Logic simulation and/or emulation which follows hardware semantics

Branch target buffer with entry source field for use in determining replacement priority

Efficient extraction of execution sets from fetch sets

Copying data to a cache using direct memory access

On-demand allocation of cache memory for use as a preset buffer

Biquad infinite impulse response system transformation

Intra-prediction mode selection while encoding a picture

DUBROVIN LEONID

Method and apparatus for caching prefetched data

Cache prefetch learning

Implementation of negation in a multiplication operation without post-incrementation

Fully asynchronous direct memory access controller and processor work

Orthogonal variable spreading factor code sequence generation

Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present

Method and apparatus to perform floating point operations

ALEXANDRON NIMROD

Low access time indirect memory accesses

Sequentially packing mask selected bits from plural words in circularly coupled register pair for transferring filled register bits to memory

Controller and method for statistical allocation of multichannel direct memory access bandwidth

Representation of data relative to varying thresholds

AMITAY AMICHAY

Adjusting direct memory access transfers used in video decoding

Cache prefetch during motion estimation

Multi-destination direct memory access transfer

LSI CORP

Reducing a degree of a polynomial in a polynomial division calculation

KALFON SHAI

Turbo parallel concatenated convolutional code implementation on multiple-issue processor cores