Inventor
BALARIN FELICE
US5 patents
Patents
5 patentsUS5954792ASep 21, 1999
Method for schedule validation of embedded systems
CADENCE DESIGN SYSTEMS INC20 citations80
US9524366B1Dec 20, 2016
Annotations to identify objects in design generated by high level synthesis (HLS)
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US8352906B2Jan 8, 2013
Method, system, and computer program product for implementing external domain independent modeling framework in a system design
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US6397371B1May 28, 2002
Procedure for worst-case analysis of discrete systems
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US7853903B1Dec 14, 2010
Method and mechanism for performing simulation off resolution proof
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