Inventor

SHEAFFER GAD S

IL33 patents

⚠️ This page may combine multiple inventors who share the name “SHEAFFER GAD S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEAFFER GAD S

INTEL CORP

Instruction dependency chain indentifier

Method and apparatus for varying energy per instruction according to the amount of available parallelism

Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters

Method of branch prediction using loop counters

Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor

System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units

Instruction set extension using operand bearing NOP instructions

Method and apparatus to execute a memory maintenance operation during a screen blanking interval

Method and apparatus for pre-processing instructions for a processor

Method and apparatus for dividing a store operation into pre-fetch and store micro-operations

Method and apparatus for constructing a pre-scheduled instruction cache

Computer for performing non-restoring division

Division algorithm for floating point or integer numbers

Method and apparatus for performing sequential executions of elements in cooperation with a transform

Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers

Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs

Method and system to overlap pointer load cache misses

Pre-steering register renamed instructions to execution unit associated locations in instruction cache

Reducing the length of lower level instructions by splitting and recombining an immediate

Display of images from tiled memory

Managing prefetching from a data buffer

Buffer pre-loading for memory service interruptions

Method and apparatus for pre-processing instructions for a processor

Technique for using memory attributes

Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs

Add-compare-select accelerator using pre-compare-select-add operation

Method and system of handling non-aligned memory accesses

EMPIRE TECHNOLOGY DEV LLC

Scheduling computing tasks for multi-processor systems based on resource requirements

Remotely controlled crowd-sourced media capture

Instance monitor

Augmented reality alteration detector

Augmented reality alteration detector

JACOBSON QUINN A

Technique for using memory attributes