Inventor

LAURENT CHRISTOPHE VINCENT ANTOINE

IT47 patents

⚠️ This page may combine multiple inventors who share the name “LAURENT CHRISTOPHE VINCENT ANTOINE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAURENT CHRISTOPHE VINCENT ANTOINE

MICRON TECHNOLOGY INC

Active boundary quilt architecture memory

Efficient utilization of memory die area

Efficient utilization of memory die area

Active boundary quilt architecture memory

Apparatus and methods for leakage current reduction in integrated circuits

Apparatus and methods for leakage current reduction in integrated circuits

Apparatus and methods for leakage current reduction in integrated circuits

Apparatus and methods for leakage current reduction in integrated circuits

Shared decoder architecture for three-dimensional memory arrays

Parallel access in a memory array

Generating a protected and balanced codeword

Generating a protected and balanced codeword

Balancing data for storage in a memory device

Architecture-based power management for a memory device

Generating a balanced codeword protected by an error correction code

Apparatus and methods for leakage current reduction in integrated circuits

Bank configurable power modes

Fast multi-payload-length error-correcting system and methods

Fast multi-payload-length error-correcting system and methods

Generating a protected and balanced codeword

Balanced codewords for reducing a selected state in memory cells

Parallel access in a memory array

Shared decoder architecture for three-dimensional memory arrays

Circuit partitioning for a memory device

Memory device with data scrubbing capability and methods

Bank configurable power modes

Generating a protected and balanced codeword

Architecture-based power management for a memory device

Shared error correction coding circuitry

Balancing data for storage in a memory device

Generating a balanced codeword protected by an error correction code

Active boundary quilt architecture memory

Efficient utilization of memory die area

Input/output line sharing for memory arrays

Circuit partitioning for a memory device

Efficient utilization of memory die area

Memory array seasoning

ECC power consumption optimization in memories

Providing multiple error correction code protection levels in memory

Fixed weight codewords for ternary memory cells

Active boundary quilt architecture memory

Apparatus and methods for leakage current reduction in integrated circuits

Power domain switches for switching power reduction

Performing sense operations in memory

Timing violation handling in a synchronous interface memory

LODESTAR LICENSING GROUP LLC

Architecture-based power management for a memory device

FERRARIO MARCO

Timing violation handling in a synchronous interface memory