Inventor

SOTO GONZALEZ JAVIER

US23 patents

⚠️ This page may combine multiple inventors who share the name “SOTO GONZALEZ JAVIER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SOTO GONZALEZ JAVIER

INTEL CORP

Methods of forming sensor integrated packages and structures formed thereby

Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling

Panel level fabrication of package substrates with integrated stiffeners

Semiconductor package with embedded die and its methods of fabrication

Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers

Die interconnect substrate, an electrical device, and a method for forming a die interconnect substrate

Bendable and stretchable electronic devices and methods

Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same

High performance integrated RF passives using dual lithography process

Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling

High performance integrated RF passives using dual lithography process

Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same

Package power delivery using plane and shaped vias

Semiconductor packaging with high density interconnects

Package power delivery using plane and shaped vias

Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers

Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages

Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers

Method for making a flexible wearable circuit

Pad-less interconnect for electrical coreless substrate

Forming die backside coating structures with coreless packages

Stretchable electronic assembly

TAHOE RES LTD

Semiconductor packaging with high density interconnects