Inventor
LAI JIUN REN
TW12 patents
⚠️ This page may combine multiple inventors who share the name “LAI JIUN REN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MACRONIX INT CO LTD
7 patentsUS6734107B2May 11, 2004
Pitch reduction in semiconductor fabrication
MACRONIX INT CO LTD322 citations98
US6518103B1Feb 11, 2003
Method for fabricating NROM with ONO structure
MACRONIX INT CO LTD11 citations72
US6849526B2Feb 1, 2005
Method of improving device resistance
MACRONIX INT CO LTD6 citations69
US6492214B2Dec 10, 2002
Method of fabricating an insulating layer
MACRONIX INT CO LTD3 citations62
US6720629B2Apr 13, 2004
Structure of a memory device with buried bit line
MACRONIX INT CO LTD1 citations48
US6787408B2Sep 7, 2004
Method for forming an electrical insulating layer on bit lines of the flash memory
MACRONIX INT CO LTD0 citations41
US6537917B2Mar 25, 2003
Method for fabricating electrically insulating layers
MACRONIX INT CO LTD0 citations41
TAIWAN SEMICONDUCTOR MFG CO LTD
3 patentsUS12266612B2Apr 1, 2025
Method for forming a semiconductor device including forming a first interconnect structure on one side of a substrate having first metal feature closer the substrate than second metal feature and forming first and second tsv on other side of substrate connecting to the metal features
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations75
US11854990B2Dec 26, 2023
Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second die
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US10923431B2Feb 16, 2021
Method for forming a 3D IC architecture including forming a first die on a first side of a first interconnect structure and a second die in an opening formed in a second side
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62