Inventor

BU HUIMING

US95 patents

⚠️ This page may combine multiple inventors who share the name “BU HUIMING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BU HUIMING

IBM

Recessed metal liner contact with copper fill

Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor

Bottom source/drain silicidation for vertical field-effect transistor (FET)

Cutting fins and gates in CMOS devices

Asymmetric multi-gate finFET

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Forming a sacrificial liner for dual channel devices

CMOS transistors with differential oxygen content high-k dielectrics

Methods and structures for forming field-effect transistors (FETs) with low-k spacers

Forming a sacrificial liner for dual channel devices

Integrating a junction field effect transistor into a vertical field effect transistor

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Vertical FET structure

Forming eDRAM unit cell with VFET and via capacitance

Electrostatic discharge devices and methods of manufacture

Dielectric isolated SiGe fin on bulk substrate

Recessed metal liner contact with copper fill

Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes

Electrostatic discharge devices and methods of manufacture

Electrostatic discharge devices and methods of manufacture

CMOS transistors with differential oxygen content high-K dielectrics

Direct contact between high-κ/metal gate and wiring process flow

Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs

Precise junction placement in vertical semiconductor devices using etch stop layers

Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs

Backside power rails and power distribution network for density scaling

Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression

Bottom source/drain silicidation for vertical field-effect transistor (FET)

Vertical transistor device

Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Vertical FET structure

Forming a sacrificial liner for dual channel devices

Electrostatic discharge protection using vertical fin CMOS technology

Electrostatic discharge devices and methods of manufacture

Dielectric isolated SiGe fin on bulk substrate

HDP fill with reduced void formation and spacer damage

Conformal doping for punch through stopper in fin field effect transistor devices

Precise junction placement in vertical semiconductor devices using etch stop layers

BASKER VEERARAGHAVAN S

Cut-very-last dual-epi flow

SOI FinFET with recessed merged Fins and liner for enhanced stress coupling

Cut-very-last dual-EPI flow

Method for fabricating finFET with merged fins and vertical silicide

SOI FinFET with recessed merged fins and liner for enhanced stress coupling

finFET with merged fins and vertical silicide

BRYANT ANDRES

FinFET structure having fully silicided fin

ANDO TAKASHI

Source-drain extension formation in replacement metal gate transistor device

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Forming a sacrificial liner for dual channel devices

TESSERA INC

Forming a sacrificial liner for dual channel devices

ST MICROELECTRONICS INC

Method of making a semiconductor device including an all around gate