Inventor

RYAN ERROL TODD

US53 patents

⚠️ This page may combine multiple inventors who share the name “RYAN ERROL TODD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RYAN ERROL TODD

GLOBALFOUNDRIES INC

Method for manufacturing fully aligned via structures having relaxed gapfills

Devices and methods of forming low resistivity noble metal interconnect

Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias

Integrated circuits and methods for fabricating integrated circuits with self-aligned vias

Methods of producing integrated circuits with an air gap

Methods of self-forming barrier integration with pore stuffed ULK material

Methods for fabricating integrated circuits having embedded electrical interconnects

Methods for fabricating integrated circuits having confined epitaxial growth regions

Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device

Etch profile control during skip via formation

Metallization levels and methods of making thereof

Methods of forming an improved via to contact interface by selective formation of a conductive capping layer

Interconnects formed by a metal displacement reaction

Liner recess for fully aligned via

Non-mandrel cut formation

Via and skip via structures

Methods for forming copper diffusion barriers for semiconductor interconnect structures

Methods for fabricating integrated circuits using surface modification to selectively inhibit etching

Methods for integration of pore stuffing material

Via and skip via structures

Multi-silicide system in integrated circuit technology

Devices and methods of forming low resistivity noble metal interconnect

Skip via structures

Interconnects formed by a metal replacement process

Skip via structures

Integrated circuits including modified liners and methods for fabricating the same

Formation of IC structure with pair of unitary metal fins

Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer

Barrier layer conformality in copper interconnects

Methods of forming conductive structures using a sacrificial liner layer

Devices and methods of forming asymmetric line/space with barrierless metallization

Copper based nitride liner passivation layers for conductive copper structures

Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device

ADVANCED MICRO DEVICES INC

Method for forming openings for conductive interconnects

Method for forming copper interconnects

Contact liner in integrated circuit technology

Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques

Contact each methodology and integration scheme

Test structure for providing depth of polish feedback

Multi-silicide in integrated circuit technology

Low stress sidewall spacer in integrated circuit technology

Conversion of transition metal to silicide through back end processing in integrated circuit technology

Method for forming a low-k dielectric structure on a substrate

INTERMOLECULAR INC

Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition

Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HCI solution

Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/H2SO4 solution

Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution

ADVANCEDMICRO DEVICES INC

Method for forming conductive interconnects

FREESCALE SEMICONDUCTOR INC

Method and structure for low-k dielectric constant applications

INTEL CORP

Device, method and system to prevent pattern collapse in a semiconductor structure