P

Inventor

ALEXANDER ALAN GRAHAM

GB32 patents

Patents

32 patents
US11321272B2May 3, 2022

Instruction set

GRAPHCORE LTD3 citations73
US10936008B2Mar 2, 2021

Synchronization in a multi-tile processing array

GRAPHCORE LTD2 citations73
US10564970B2Feb 18, 2020

Synchronization in a multi-tile processing arrangement

GRAPHCORE LTD3 citations72
US10558595B2Feb 11, 2020

Sending data off-chip

GRAPHCORE LTD4 citations72
US11449338B2Sep 20, 2022

Handling exceptions in a multi-tile processing arrangement

GRAPHCORE LTD2 citations71
US11467833B2Oct 11, 2022

Load-store instruction for performing multiple loads, a store, and strided increment of multiple addresses

GRAPHCORE LTD3 citations70
US11567768B2Jan 31, 2023

Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times

GRAPHCORE LTD2 citations68
US12141092B2Nov 12, 2024

Instruction set

GRAPHCORE LTD0 citations62
US11709794B2Jul 25, 2023

Exchange between stacked die

GRAPHCORE LTD1 citations62
US11593185B2Feb 28, 2023

Synchronization in a multi-tile processing arrangement

GRAPHCORE LTD0 citations62
US11586483B2Feb 21, 2023

Synchronization amongst processor tiles

GRAPHCORE LTD0 citations62
US11416440B2Aug 16, 2022

Controlling timing in computer processing

GRAPHCORE LTD0 citations62
US11262787B2Mar 1, 2022

Compiler method

GRAPHCORE LTD0 citations62
US11023290B2Jun 1, 2021

Synchronization amongst processor tiles

GRAPHCORE LTD1 citations62
US10963003B2Mar 30, 2021

Synchronization in a multi-tile processing array

GRAPHCORE LTD1 citations62
US10802536B2Oct 13, 2020

Compiler method

GRAPHCORE LTD1 citations62
US10628377B2Apr 21, 2020

Synchronization in a multi-tile processing arrangement

GRAPHCORE LTD1 citations62
US11893390B2Feb 6, 2024

Method of debugging a processor that executes vertices of an application, each vertex being assigned to a programming thread of the processor

GRAPHCORE LTD0 citations61
US11416258B2Aug 16, 2022

Method of debugging a processor that executes vertices of an application, each vertex being assigned to a programming thread of the processor

GRAPHCORE LTD0 citations61
US11023413B2Jun 1, 2021

Synchronization in a multi-tile, multi-chip processing arrangement

GRAPHCORE LTD1 citations61
US11169777B2Nov 9, 2021

Multiple modes for handling overflow conditions resulting from arithmetic operations

GRAPHCORE LTD1 citations60
US10705999B1Jul 7, 2020

Exchange of data between processor modules

GRAPHCORE LTD0 citations52
US10705998B1Jul 7, 2020

Exchange of data between processor modules

GRAPHCORE LTD0 citations52
US10579582B2Mar 3, 2020

Controlling timing in computer processing

GRAPHCORE LTD0 citations52
US10817444B2Oct 27, 2020

Sending data from an arrangement of processor modules

GRAPHCORE LTD0 citations51
US11775415B2Oct 3, 2023

Debugging instruction register to receive and input debugging instructions to a processor for a thread of execution in a debug mode

GRAPHCORE LTD0 citations50
US11645081B2May 9, 2023

Handling exceptions in a multi-tile processing arrangement

GRAPHCORE LTD0 citations50
US11169778B2Nov 9, 2021

Converting floating point numbers to reduce the precision

GRAPHCORE LTD0 citations50
US10579585B2Mar 3, 2020

Synchronization in a multi-tile, multi-chip processing arrangement

GRAPHCORE LTD0 citations50
US12367043B2Jul 22, 2025

Multi-threaded barrel processor using shared weight registers in a common weights register file

GRAPHCORE LTD0 citations49
US11061679B2Jul 13, 2021

Double-load instruction using a fixed stride and a variable stride for updating addresses between successive instructions

GRAPHCORE LTD0 citations49
US12013781B2Jun 18, 2024

Processing device using variable stride pattern

GRAPHCORE LTD0 citations47