Inventor

LI YENLUNG

US25 patents

⚠️ This page may combine multiple inventors who share the name “LI YENLUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI YENLUNG

SANDISK TECHNOLOGIES LLC

Non-volatile memory with reduced data cache buffer

Non-volatile memory with fast data cache transfer scheme

Centralized variable rate serializer and deserializer for bad column management

Centralized variable rate serializer and deserializer for bad column management

Dynamic word line reconfiguration for NAND structure

On-the-fly compression scheme for soft bit data in non-volatile memory

Robust storage of bad column data and parity bits on word line

Low latency data transfer

Asynchronous FIFO buffer for redundant columns in memory device

Use of data latches for plane level compression of soft bit data in non-volatile memories

Vertical compression scheme for compressed soft bit data in non-volatile memories with data latch groups

Architecture and data path options for compression of soft bit data in non-volatile memories

On-the-fly multiplexing scheme for compressed soft bit data in non-volatile memories

Circuits and methods for reliable replacement of bad columns in a memory device

Use of data latches for compression of soft bit data in non-volatile memories

Non-volatile memory with shared data transfer latches

Non-volatile storage system with power on read timing reduction

Centralized fixed rate serializer and deserializer for bad column management in non-volatile memory

SANDISK TECHNOLOGIES INC

Sense amplifier with efficient use of data latches

Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period

Adaptive selective bit line pre-charge for current savings and fast programming

Built-in self-test circuitry for data in path for non-volatile memory with multiple test clock speeds for multiple test modes

WESTERN DIGITAL TECH INC

Overhead reduction in data transfer protocol for NAND memory

Overhead reduction in data transfer protocol for NAND memory

Circuit to reduce gating overall system performance