Inventor

HASENPLAUGH WILLIAM C

US31 patents

⚠️ This page may combine multiple inventors who share the name “HASENPLAUGH WILLIAM C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HASENPLAUGH WILLIAM C

INTEL CORP

Variable precision floating point multiply-add circuit

Multiplying two numbers

Dynamic quality of service (QoS) for a shared cache

System and method for cryptography processing units and multiplier

Scalable multi-layer 2D-mesh routers

Hardware compilation and/or translation with fault detection and roll back functionality

Low energy consumption mantissa multiplication for floating point multiply-add operations

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Update mask for handling interaction between fills and updates

Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Determining message residue using a set of polynomials

Distributed power management for multi-core processors

Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit

Address range priority mechanism

Techniques for merging tables

Hardware apparatuses and methods to control cache line coherency

Multicast tree-based data distribution in distributed shared cache

STEELY JR SIMON C

Cache spill management techniques using cache spill prediction

Efficient support of sparse data structure access

Signature based hit-predicting cache

Short circuit of probes in a chain

Domain state

Method and apparatus for optimizing the usage of cache memories

Retrieval of previously accessed data in a multi-core processor

Probe speculative address file

High bandwidth full-block write commands

FEGHALI WAJDI K

Cryptographic system, method and multiplier

HASENPLAUGH WILLIAM C

Modular reduction using folding

STEELY JR SIMON

Address range priority mechanism

CHEE NICHOLAS CHENG HWA

Hardware compilation and/or translation with fault detection and roll back functionality