Inventor

STEELY JR SIMON C

US112 patents

⚠️ This page may combine multiple inventors who share the name “STEELY JR SIMON C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEELY JR SIMON C

DIGITAL EQUIPMENT CORP

Mechanism for reducing latency of memory barrier operations on a multiprocessor system

Multi instruction register mapper

Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery

High performance recoverable communication method and apparatus for write-only networks

Trainable apparatus for predicting instruction outcomes in pipelined processors

Next line prediction apparatus for a pipelined computed system

Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline

Past-history filtered branch prediction

Past-history filtered branch prediction

Multiple block line prediction

Ring based distributed communication bus for a multiprocessor network

Multi-index multi-way set-associative cache

Cache memory system

Apparatus and method for intelligent multiple-probe cache allocation

Memory reference tagging

System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command

Cache with at least two fill rates

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for adaptively bypassing one or more levels of a cache hierarchy

System and method for providing parallel data requests

System and method for responses between different cache coherency protocols

Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation

System and method for updating owner predictors

Transaction references for requests in a multi-processor network

System and method to facilitate ordering point migration

Systems and methods for employing speculative fills

System and method for conflict responses in a cache coherency protocol with ordering point migration

Source request arbitration

Managing a multi-way associative cache

System and method for blocking data responses

System and method for read migratory optimization in a cache coherency protocol

COMPAQ COMPUTER CORP

Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches

Mechanism for optimizing generation of commit-signals in a distributed shared-memory system

Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor

Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches

System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction

High-performance non-blocking switch with multiple channel ordering constraints

Victimization of clean data blocks

Method and apparatus for releasing victim data buffers of computer systems by comparing a probe counter with a service counter

High-performance communication method and apparatus for write-only networks

Independent victim data buffer and probe buffer release control utilzing control flag

Adaptive dirty-block purging

INTEL CORP

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Dynamic quality of service (QoS) for a shared cache

Processors and methods for pipelined runtime services in a spatial array

Processors, methods, and systems for debugging a configurable spatial accelerator

Processors, methods, and systems with a configurable spatial accelerator

STEELY JR SIMON C

Cache spill management techniques using cache spill prediction

Consistency evaluation of program execution across at least one memory barrier

DIGITAL EQUIPMENT

Set prediction cache memory system using bits of the main memory address