Inventor

CHARNEY MARK

US62 patents

⚠️ This page may combine multiple inventors who share the name “CHARNEY MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHARNEY MARK

INTEL CORP

Floating point to fixed point conversion

Fixed point to floating point conversion

Apparatus and method for complex by complex conjugate multiplication

Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data

Apparatus and method for multiplying, summing, and accumulating sets of packed bytes

Fixed point to floating point conversion

Vector friendly instruction format and execution thereof

Apparatus and method for vector multiply and accumulate of packed bytes

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatus and method for vector multiply and accumulate of packed words

Apparatus and method for scaling pre-scaled results of complex multiply-accumulate operations on packed real and imaginary data elements

Apparatus and method for multiply, add/subtract, and accumulate of packed data elements

Floating point to fixed point conversion

Apparatus and method for converting a floating-point value from half precision to single precision

Apparatus and method for vector multiply and accumulate of unsigned doublewords

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

Apparatus and method for complex multiply and accumulate

Apparatus and method for complex multiplication

Apparatus and method for vector packed signed/unsigned shift, round, and saturate

Apparatus and method for converting a floating-point value from half precision to single precision

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatus and method for complex multiplication

Instructions to convert from FP16 to BF8

Instructions to convert from FP16 to BF8

Apparatuses, methods, and systems for instructions for matrix multiplication instructions

Copy a subset of status flags from a control and status register to a flags register

Apparatus and method for complex multiplication

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

Apparatus and method for complex by complex conjugate multiplication

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

Apparatus and method for complex multiplication

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

Apparatus and method for multiplication and accumulation of complex and real packed data elements

Apparatus and method for vector multiply and accumulate of signed doublewords

Apparatus and method for shifting quadwords and extracting packed words

Apparatuses, methods, and systems for instructions for downconverting a tile row and interleaving with a register

BFLOAT16 fused multiply instructions

Instruction and logic for sum of square differences

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Instructions to convert from FP16 to BF8

Apparatus and method for vector horizontal add of signed/unsigned words and doublewords

Apparatus and method for performing dual signed and unsigned multiplication of packed data elements

IBM

Branch history guided instruction/data prefetching

Prefetching using future branch path information derived from branch prediction

Methods for caching cache tags

TOLL BRET L

Packed data operation mask comparison processors, methods, systems, and instructions