Inventor

MISHAELI MICHAEL

IL48 patents

⚠️ This page may combine multiple inventors who share the name “MISHAELI MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MISHAELI MICHAEL

INTEL CORP

Processor core power event tracing

Memory copy instructions, processors, methods, and systems

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Hardware mechanism for performing atomic actions on remote processors

Forcing a processor into a low power state

Method for booting a heterogeneous system and presenting a symmetric core view

Method and apparatus for determining thread execution parallelism

Changing the clock frequency of a computing device

Conditional memory fault assist suppression

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Methods, apparatus, and instructions for user-level thread suspension

Methods, apparatus, and instructions for user level thread suspension

System and method for communication using a register management array circuit

Apparatus and method for detecting and recovering from data fetch errors

Apparatus and method for detecting and recovering from data fetch errors

Forcing a processor into a low power state

Instruction and logic for store broadcast and power management

System, apparatus and method for probeless field scan of a processor

Error reporting and handling using a common error handler

System and method for communication using a register management array circuit

Extension of CPU context-state management for micro-architecture state

Local power gate (LPG) interfaces for power-aware operations

Flushing and restoring core memory content to external memory

Optimizing performance of instructions based on sequence detection or information associated with the instructions

Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach

Branch prediction unit in service of short microcode flows

Method for booting a heterogeneous system and presenting a symmetric core view

Compacted context state management

Processor core power event tracing

Systems, apparatuses, and methods for autonomous functional testing of a processor

Thread pause processors, methods, systems, and instructions

YIGZAW THEODROS

Apparatus and method for implement a multi-level memory hierarchy

Apparatus and method for detecting and recovering from data fetch errors

FALIK OHAD

Mechanism for facilitating faster suspend/resume operations in computing systems

Optimizing performance of instructions based on sequence detection or information associated with the instructions

MISHAELI MICHAEL

Managing and tracking thread access to operating system extended features using map-tables containing location references and thread identifiers

Local power gate (LPG) interfaces for power-aware operations

GINZBURG BORIS

Providing an asymmetric multicore processor system transparently to an operating system

SODHI INDER M

Execution context swap between heterogeneous functional hardware units

ROTEM EFRAIM

Extension of CPU context-state management for micro-architecture state

NAVEH ALON

Migrating tasks between asymmetric computing elements of a multi-core processor

VAN DYKE DON A

Context state management for processor feature sets

YAMADA KOICHI

Core switching acceleration in asymmetric multiprocessor system

SPERBER ZEEV

Recoverable parity and residue error

TAHOE RES LTD

Compacted context state management

VAN DYKE DON

Context state management for processor feature sets