Inventor

CHANG TZONG-SHENG

TW36 patents

⚠️ This page may combine multiple inventors who share the name “CHANG TZONG-SHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG TZONG-SHENG

TAIWAN SEMICONDUCTOR MFG

Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)

Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence

Method of forming and etching a resist protect oxide layer including end-point etch

Method to improve TiSix salicide formation

Fabrication process for MOSFET devices and a reproducible capacitor structure

Fabrication process for MOSFET devices and a reproducible capacitor structure

Method of increasing end point detection capability of reactive ion etching by adding pad area

Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits

Non-distort spacer profile during subsequent processing

Bond pad scheme for Cu process

Methods for forming a semiconductor arrangement with structures having different heights

Bond pad scheme for Cu process

Method for salicide process using a titanium nitride barrier layer

Method to reduce leakage in a protection diode structure

Semiconductor device with reduced leakage protection diode

Method for forming interconnect structure

Semiconductor device having a spacer and a liner overlying a sidewall of a gate structure and method of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD

Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures

Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies

Method of fabricating reticle

Methods for manufacturing semiconductor arrangements using photoresist masks

Method of fabricating reticle

Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool

Semiconductor arrangement having an overlay alignment mark with a height shorter than a neighboring gate structure

Method for forming semiconductor device structure

Method of fabricating reticle

Semiconductor structure with data storage structure and method for manufacturing the same

Method for forming interconnect structure

Methods and apparatus of metal gate transistors

Semiconductor structure with data storage structure

Method of manufacturing a semiconductor structure including a plurality of trenches

Semiconductor device structure and method for forming the same

Method for forming interconnect structure

Method for forming interconnect structure

LIN CHENG-TE

Reacted layer for improving thickness uniformity of strained structures

TAIWAN SEMICONDUCTOR MANUFACTRING COMPANY LTD

Methods and apparatus of metal gate transistors