Inventor

KIM KANG-YONG

US164 patents

⚠️ This page may combine multiple inventors who share the name “KIM KANG-YONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM KANG-YONG

MICRON TECHNOLOGY INC

Delay stage-interweaved analog DLL/PLL

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for duty cycle error correction of clock signals

Apparatuses and methods for duty cycle distortion correction of clocks

Apparatuses and methods including memory commands for semiconductor memories

Method and apparatus for high resolution ZQ calibration

Method and apparatus for high resolution ZQ calibration

Control of a variable delay line using line entry point to modify line power supply voltage

Method and apparatus for output driver calibration

DLL phase detection using advanced phase equalization

Delay-locked loop having a pre-shift phase detector

Method and apparatus for digital phase generation at high frequencies

Delay-locked loop having a pre-shift phase detector

Delay-locked loop having a pre-shift phase detector

System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits

Delay stage-interweaved analog DLL/PLL

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods including multilevel command and address signals

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal

Apparatuses and methods for duty cycle error correction of clock signals

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal

Apparatuses and methods for reducing cycle times in successive memory accesses

Seamless coarse and fine delay structure for high performance DLL

Apparatus and method for trimming static delay of a synchronizing circuit

Delay line circuit

Method and apparatus for digital phase generation at high frequencies

Automated error correction with memory refresh

Shared error correction code (ECC) circuitry

Adaptive memory registers

Apparatus and method for trimming static delay of a synchronizing circuit

Delay stage-interweaved analog DLL/PLL

HYUNDAI ELECTRONICS IND

Method and device for automatically performing refresh operation in semiconductor memory device

Pulse generating apparatus

KWAK JONGTAE

Seamless coarse and fine delay structure for high performance DLL

Seamless coarse and fine delay structure for high performance DLL

LODESTAR LICENSING GROUP LLC

Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

LI HAI

Spin-transfer torque memory self-reference read method